FIN1215MTDX Datasheet, PDF (5/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

Truth Tables
Transmitter
TxIn
Inputs
TxCLKIn
PwrDn⁽¹⁾
Outputs
TxOut±
TxCLKOut±
Active
Active
HIGH
LOW / HIGH
LOW / HIGH
Active
LOW / HIGH
High Impedance
HIGH
LOW / HIGH
Don’t Care⁽²⁾
Floating
Floating
Active
Floating
HIGH
HIGH
LOW
LOW
LOW / HIGH
Don’t Care⁽²⁾
Don’t Care
Don’t Care
LOW
High Impedance
High Impedance
Notes:
1. The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V.
2. TxCLKOut± settles at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is
a steady logic level LOW / HIGH / high-impedance.
Receiver
RxIn±
Inputs
RxCLKIn±
/PwrDn⁽³⁾
Outputs
RxOut
RxCLKOut
Active
Active
Failsafe Condition⁽⁴⁾
Failsafe Condition⁽⁴⁾
Active
Failsafe Condition⁽⁴⁾
Active
Failsafe Condition⁽⁴⁾
HIGH
HIGH
HIGH
HIGH
LOW / HIGH
Last Valid State
HIGH
Last Valid State⁽⁵⁾
LOW / HIGH
HIGH
LOW / HIGH
HIGH
Don’t Care
Don’t Care
LOW
LOW
HIGH
Notes:
3. The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V.
4. Failsafe condition is defined as the input being terminated and un-driven, shorted, or open.
5. If RxCLKIn± is removed prior to the RxIn± date being removed, RxOut is the last valid state. If RxIn± data is
removed prior to RxCLKIn± being removed, RxOut is HIGH.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
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