FIN1215MTDX Datasheet, PDF (18/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

AC Loadings and Waveforms (Continued)
Note: tRSKM is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI).
The minimum and maximum pulse position values are based on the bit position of each of the seven bits within
the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).
Figure 22. Receiver LVDS Input Skew Margin
Note: This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with
worst jitter ±ns (cycle-to-cycle) clock input. The specific test methodology is as follows:
ƒ Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to
the right +3ns when data is HIGH (by switching between CLK1 and CLK2 in Figure 11).
ƒ The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources.
Jumping between two clock sources to simulate the worst-case of clock edge jump (3ns) from
graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range
with 100mV noise (VCC noise frequency <2MHz).
Figure 23. Jitter Pattern
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
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