FIN1215MTDX Datasheet, PDF (1/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

September 2009
FIN1215 / FIN1216 / FIN1217/ FIN1218
LVDS 21-Bit Serializers / De-Serializers
Features
ƒ Low Power Consumption
ƒ 20MHz to 85MHz Shift Clock Support
ƒ 50% Duty Cycle on the Clock Output of Receiver
ƒ ±1V Common-mode Range ~1.2V
ƒ Narrow Bus Reduces Cable Size and Cost
ƒ High Throughput: 1.785Gbps
ƒ Up to 595Mbps per Channel
ƒ Internal PLL with No External Components
ƒ Compatible with TIA/EIA-644 Specification
ƒ Offered in 48-lead TSSOP Packages
Description
The FIN1217 and FIN1215 transform 21-bit wide
parallel LVTTL (Low-Voltage TTL) data into three serial
LVDS (Low-Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data stream over a separate LVDS link.
Every cycle of transmit clock, 21 bits of input LVTTL
data are sampled and transmitted.
The FIN1216 and FIN1218 receives and converts the
three serial LVDS data streams back into 21 bits of
LVTTL data. Table 1 provides a matrix summary of the
serializers and de-serializers available. For the
FIN1217, at a transmit clock frequency of 85MHz, 21
bits of LVTTL data are transmitted at a rate of 595Mbps
per LVDS channel.
These chipsets solve EMI and cable size problems
associated with wide and high-speed TTL interfaces.
Ordering Information
Operating
Part Number Temperature
Range
FIN1215MTDX
FIN1216MTDX
FIN1217MTDX ^{-40 to + 85°C}
FIN1218MTDX
(Preliminary)
Eco
Status
RoHS
Package
48-Lead Thin Shrink Small Outline Package (TSSOP)
Packing
Method
Tape and Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com