FIN1215MTDX Datasheet, PDF (13/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

Test Circuits
Figure 5. Differential LVDS Output DC Test Circuit
Notes: For all input pulses, tR or tF<=1ns.
CL includes all probe and jig capacitance.
Figure 6. Differential Receiver Voltage Definitions, Propagation Delay, and Transition Time Test Circuit
Table 2.
Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
Resulting Differential
Input Voltage (mV)
V_IA
1.25
1.15
2.40
2.30
0.10
0
1.50
0.90
2.40
1.80
0.60
0
V_IB
1.15
1.25
2.30
2.40
0
0.10
0.90
1.50
1.80
2.40
0
0.60
V_ID
100
-100
100
-100
100
-100
600
-600
600
-600
600
-600
Resulting Common
Mode Input Voltage (V)
V_IC
1.20
1.20
2.35
2.35
0.05
0.05
1.20
1.20
2.10
2.10
0.30
0.30
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
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