FIN1215MTDX Datasheet, PDF (3/20 Pages) Fairchild Semiconductor – LVDS 21-Bit Serializers / De-Serializers

Transmitters
Pin Configuration
Figure 3. FIN1217 / FIN1215 (21:3 Transmitter)
Pin Definitions
Pin Names
TxIn
TxCKLIn
TxOut+
TxOut
TxCLKOut+
TxCLKOut-
/PwrDn
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
GND
NC
I/O
Type
I
I
O
O
O
O
I
I
I
I
I
I
I
# of
Pins
21
1
3
3
1
1
1
1
2
1
3
4
5
Description of Signals
LVTTL Level Inputs
LVTTL Level Clock Input; the rising edge is for data strobe
Positive LVDS Differential Data Output
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
LVTTL Level Power-Down Input; assertion (LOW) puts the outputs in high-
impedance state
Power Supply Pin for LVDS Outputs
Ground Pins for PLL
Power Supply Pins for LVDS Outputs
Ground Pin for LVDS Outputs
Power Supply Pins for LVTTL Inputs
Ground Pins for LVTTL Inputs
No Connect
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
3
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