ACE1502 Datasheet, PDF(9/33 Page) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

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ACE1502 Datasheet, PDF (9/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

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subroutine is ï¬nished, a return from subroutine (RET)

instruction is executed. The RET instruction pulls the previously

stacked return address from the stack and loads it into the

program counter. Execution then continues at the recovered

return address.

3.1.5 Status Register (SR)

The 8-bit Status register (SR) contains four condition code indi-

cators (C, H, Z, and N), one interrupt masking bit (G), and an

EEPROM write ï¬ag (R.) The condition codes are automatically

updated by most instructions. (See Table 9.)

Carry/Borrow (C)

The carry ï¬ag is set if the arithmetic logic unit (ALU) performs a

carry or borrow during an arithmetic operation and by its dedi-

cated instructions. The rotate instruction operates with and

through the carry bit to facilitate multiple-word shift operations.

The LDC and INVC instructions facilitate direct bit manipulation

using the carry ï¬ag.

Half Carry (H)

The half carry ï¬ag indicates whether an overï¬ow has taken

place on the boundary between the two nibbles in the accumu-

lator. It is primarily used for Binary Coded Decimal (BCD) arith-

metic calculation.

Zero (Z)

The zero ï¬ag is set if the result of an arithmetic, logic, or data

manipulation operation is zero. Otherwise, it is cleared.

Negative (N)

The negative ï¬ag is set if the MSB of the result from an arith-

metic, logic, or data manipulation operation is set to one. Other-

wise, the ï¬ag is cleared. A result is said to be negative if its MSB

is a one.

Interrupt Mask (G)

The interrupt request mask (G) is a global mask that disables all

maskable interrupt sources. If the G Bit is cleared, interrupts

can become pending, but the operation of the core continues

uninterrupted. However, if the G Bit is set an interrupt is recog-

nized. After any reset, the G bit is cleared by default and can

only be set by a software instruction. When an interrupt is rec-

ognized, the G bit is cleared after the PC is stacked and the

interrupt vector is fetched. Once the interrupt is serviced, a

Figure 13. Basic Interrupt Structure

return from interrupt instruction is normally executed to restore

the PC to the value that was present before the interrupt

occurred. The G bit is the reset to one after a return from inter-

rupt is executed. Although the G bit can be set within an inter-

rupt service routine, ânestingâ interrupts in this way should only

be done when there is a clear understanding of latency and of

the arbitration mechanism.

3.2 Interrupt handling

When an interrupt is recognized, the current instruction com-

pletes its execution. The return address (the current value in the

program counter) is pushed onto the stack and execution con-

tinues at the address speciï¬ed by the unique interrupt vector

(see Table 10.). This process takes ï¬ve instruction cycles. At

the end of the interrupt service routine, a return from interrupt

(RETI) instruction is executed. The RETI instruction causes the

saved address to be pulled off the stack in reverse order. The G

bit is set and instruction execution resumes at the return

address.

The ACEx microcontroller is capable of supporting four inter-

rupts. Three are maskable through the G bit of the SR and the

fourth (software interrupt) is not inhibited by the G bit (Figure

13.) The software interrupt is generated by the execution of the

INTR instruction. Once the INTR instruction is executed, the

ACEx core will interrupt whether the G bit is set or not. The

INTR interrupt is executed in the same manner as the other

maskable interrupts where the program counter register is

stacked and the G bit is cleared. This means, if the G bit was

enabled prior to the software interrupt the RETI instruction must

be used to return from interrupt in order to restore the G bit to its

previous state. However, if the G bit was not enabled prior to

the software interrupt the RET instruction must be used.

In case of multiple interrupts occurring at the same time, the

ACEx microcontroller core has prioritized the interrupts. The

interrupt priority sequence in shown in Table 7.

Table 7: Interrupt Priority Sequence

Priority (4 highest, 1 lowest) Interrupt

MIW (EDGEI)

Timer0 (TMRI0)

Timer1 (TMRI1)

Software (INTR)

INTR

MIW

T1PND

T0PND

WKPND

Interrupt

Pending

Flags

T1EN

T0INT

WKINT

Interrupt Enable Bits

Global Interrupt

Enable

Interrupt

ACE1502 Product Family Rev. 1.7

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