ACE1502 Datasheet, PDF (22/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

Figure 27. Multi-input Wakeup (MIW) Block Diagram
Data Bus
7
0
WKEN[7:0]
G0
0
WKOUT
EDGEI
G7
WKEDG[0:7]
7
WKPND[0:7]
WKINTEN ¹⁰
10. WKINTEN: Bit 7 of T0CNTRL
9. I/O Port
The eight I/O pins (six on 8-pin package option) are bi-
directional (see Figure 28). The bi-directional I/O pins can be
individually configured by software to operate as high-
impedance inputs, as inputs with weak pull-up, or as push-pull
outputs. The operating state is determined by the contents of
the corresponding bits in the data and configuration registers.
Each bi-directional I/O pin can be used for general purpose I/O,
or in some cases, for a specific alternate function determined by
the on-chip hardware.
Figure 28. PORTGD Logic Diagram
GXPULLEN
GXBUFEN
9.1 I/O registers
The I/O pins (G0-G7) have three memory-mapped port regis-
ters associated with the I/O circuitry: a port configuration regis-
ter (PORTGC), a port data register (PORTGD), and a port input
register (PORTGP). PORTGC is used to configure the pins as
inputs or outputs. A pin may be configured as an input by writing
a 0 or as an output by writing a 1 to its corresponding PORTGC
bit. If a pin is configured as an output, its PORTGD bit repre-
sents the state of the pin (1 = logic high, 0 = logic low). If the pin
is configured as an input, its PORTGD bit selects whether the
pin is a weak pull-up or a high-impedance input. Table 13 pro-
vides details of the port configuration options. The port configu-
ration and data registers can both be read from or written to.
Reading PORTGP returns the value of the port pins regardless
of how the pins are configured. Since this device supports MIW,
PORTG inputs have Schmitt triggers.
GXOUT
GX
GXIN
Figure 29. I/O Register bit assignments
Bit 7
11_G7
Bit 6
11_G6
Bit 5
G5
PORTGC, PORTGD, PORTGD
Bit 4
G4
Bit 3
12_G3
Bit 2
G2
11. Available only on the 14-pin package option
12. G3 after reset is an input with weak pull-up
Bit 1
G1
Table 13. I/O configuration options
Configuration Bit
Data Bit
0
0
0
1
1
0
1
1
Port Pin Configuration
High-impedence input (TRI-STATE input)
Input with pull-up (weak one input)
Push-pull zero output
Push-pull one output
Bit 0
G0
22
ACE1502 Product Family Rev. 1.7
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