ACE1502 Datasheet, PDF (11/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

Table 9. Instruction Cycles and Bytes
Flags
Mnemonic Operand Bytes Cycles affected
ADC
A, [X]
1
1
C,H,Z,N
ADC
A, [#,X]
2
3
C,H,Z,N
ADC
A, M
2
2
C,H,Z,N
ADC
A, #
2
2
C,H,Z,N
ADD
A, [X]
1
1
Z,N
ADD
A, [#,X]
2
3
Z,N
ADD
A, M
2
2
Z,N
ADD
A, #
2
2
Z,N
AND
A, [X]
1
1
Z,N
AND
A, [#,X]
2
3
Z,N
AND
A, M
2
2
Z,N
AND
A, #
2
2
Z,N
CLR
X
1
1
Z
CLR
A
1
1
C,H,Z,N
CLR
M
2
1
C,H,Z,N
DEC
X
1
1
Z
DEC
A
1
1
Z,N
DEC
M
2
2
Z,N
IFBIT
#, A
1
1
None
IFBIT
#, M
2
2
None
IFBIT
#, [X]
1
1
None
IFC
1
1
None
IFEQ
A, [#, X]
2
3
None
IFEQ
A, [X]
1
1
None
IFEQ
A, #
2
2
None
IFEQ
A, M
2
2
None
IFEQ
M, #
3
3
None
IFEQ
X, #
3
3
None
IFGT
A, [#, X]
2
3
None
IFGT
A, [X]
1
1
None
IFGT
A, #
2
2
None
IFGT
A, M
2
2
None
IFGT
X, #
3
3
None
IFLT
X, #
3
3
None
IFNBIT
#, A
1
1
None
IFNBIT
#, M
2
2
None
IFNBIT
#, [X]
1
1
None
IFNC
1
1
None
IFNE
A, [#, X]
2
3
None
IFNE
A, [X]
1
1
None
IFNE
A, #
2
2
None
IFNE
A, M
2
2
None
IFNE
X, #
3
3
None
IFNE
M, #
3
3
None
INC
A
1
1
Z,N
INC
M
2
2
Z,N
Mnemonic
INC
INTR
INVC
JMP
JMP
JP
JSR
JSR
LD
LD
LD
LD
LD
LD
LD
LDC
NOP
OR
OR
OR
OR
RBIT
RBIT
RC
RET
RETI
RLC
RLC
RRC
RRC
SBIT
SBIT
SC
ST
ST
ST
STC
SUBC
SUBC
SUBC
SUBC
XOR
XOR
XOR
XOR
Operand
X
M
[#, X]
M
[#, X]
A, #
A, [#,X]
A, [X]
A, M
M, #
M, M
X, #
#, M
A, [X]
A, [#,X]
A, M
A, #
#, [X]
#, M
A
M
A
M
#, [X]
#, M
A, [#,X]
A, [X]
A, M
#, M
A, [X]
A, [#,X]
A, M
A, #
A, [X]
A, [#,X]
A, M
A, #
Bytes
1
1
1
3
2
1
3
2
2
2
1
2
3
3
3
2
1
1
2
2
2
1
2
1
1
1
1
2
1
2
1
2
1
2
1
2
2
1
2
2
2
1
2
2
2
Cycles
1
5
1
4
3
1
5
5
2
3
1
2
3
3
3
2
1
1
3
2
2
2
2
1
5
5
1
2
1
2
2
2
1
3
1
2
2
1
3
2
2
1
3
2
2
Flags
affected
Z
None
C
None
None
None
None
None
None
None
None
None
None
None
None
C
None
Z, N
Z,N
Z,N
Z,N
Z,N
Z,N
C,H
None
None
C,Z,N
C,Z,N
C,Z,N
C,Z,N
Z,N
Z,N
C,H
None
None
None
Z,N
C,H,Z,N
C,H,Z,N
C,H,Z,N
C,H,Z,N
Z,N
Z,N
Z,N
Z,N
11
ACE1502 Product Family Rev. 1.7
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