ACE1502 Datasheet, PDF (20/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

Figure 22. Bit Period Configuration (BPSEL) Register
Bit 7
0
Bit 6
0
Bit 5
Bit 4
BPL[2:0]
Bit 3
Figure 23. HBC Control (HBCNTRL) Register
Bit 7
OCFLAG
Bit 6
IOSEL
Bit 5
START / STOP
Bit 4
TXBUSY
Bit 3
0
Figure 24. HBC signals for one byte message in PWM format
Condition:
BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]
DAT0 = 0x52
No. bit to encode = 8 (HBCNTRL = XXXX0111b)
TXBUSY
START/STOP
ShiftCLK
Bit 2
Bit 2
Bit 1
BPH[2:0]
Bit 1
FRAME[2:0]
Bit 0
Bit 0
OCFLAG
Bit 7
DAT0
G2/G5
Output
IR/RF
CLOCK
"0"
"0"
"1"
"0"
"1"
"0"
"0"
"1"
"0"
Figure 25. Sending series of encoded messages
Conditions:
BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]
DAT0 = 0x52 , 0x92
No. bit to encode = 8 (HBCNTRL = XXXX0111b)
TXBUSY
START/STOP
ShiftCLK
Software must set the START bit while OCFLAG is set in
order to send another message without introducing a delay.
STOP bit clear,
transmission ends.
OCFLAG
Bit 7
DAT0
G2/G5
Output
IR/RF
CLOCK
"0" "0" "1" "0" "1" "0" "0" "1" "0" "1" "0" "0" "1" "0" "0" "1" ^"0"
20
ACE1502 Product Family Rev. 1.7
www.fairchildsemi.com