ACE1502 Datasheet, PDF (18/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

6. Watchdog
The Watchdog timer is used to reset the device and safely
recover in the rare event of a processor “runaway condition.”
The 12-bit Timer 0 is used as a pre-scalar for Watchdog timer.
The Watchdog timer must be serviced before every 61,440
cycles but no sooner than 4096 cycles since the last Watchdog
reset. The Watchdog is serviced through software by writing the
value 0x1B to the Watchdog Service (WDSVR) register (see
Figure 20). The part resets automatically if the Watchdog is ser-
viced too frequent, or not frequent enough.
The Watchdog timer must be enabled through the Watchdog
enable bit (WDEN) in the initialization register. The WDEN bit
Figure 20. Watchdog Service Register (WDSVR)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
1
can only be set while the device is in programming mode. Once
set, the Watchdog will always be powered-up enabled. Software
cannot disable the Watchdog. The Watchdog timer can only be
disabled in programming mode by resetting the WDEN bit as
long as the memory write protect (WDIS) feature is not enabled.
WARNING
Ensure that the Watchdog timer has been serviced before
entering IDLE mode because it remains operational during this
time.
Bit 3
1
Bit 2
0
Bit 1
1
Bit 0
1
7. Hardware Bit-Coder
The Hardware Bit-Coder is a dedicated hardware bit-encoding
peripheral block, Hardware Bit-Coder (HBC), for IR/RF data
transmission (see Figure 21.) The HBC is completely software
programmable and can be configured to emulate various bit-
encoding formats. The software developer has the freedom to
encode each bit of data into a desired pattern and output the
encoded data at the desired frequency through either the G2 or
G5 output (TX) ports.
The HBC contains six 8-bit memory-mapped configuration reg-
isters PSCALE, HPATTERN, LPATTERN, BPSEL, HBCNTRL,
and DAT0. The registers are used to select the transmission fre-
quency, store the data bit-encoding patterns, configure the data
bit-pattern/frame lengths, and control the data transmission
flow.
To select the IR/RF transmission frequency, an 8-bit divide con-
stant must be written into the IR/RF Pre-scalar (PSCALE) regis-
ter. The IR/RF transmission frequency generator divides the
1MHz instruction clock down by 4 and the PSCALE register is
used to select the desired IR/RF frequency shift. Together, the
transmission frequency range can be configured between
976Hz (PSCALE = 0xFF) and 125kHz (PSCALE = 0x01). Upon
a reset, the PSCALE register is initialized to zero disabling the
IR/RF transmission frequency generator. However, once the
PSCALE register is programmed, the desired IR/RF frequency
is maintained as long as the device is powered.
Once the transmission frequency is selected, the data bit-
encoding patterns must be stored in the appropriate registers.
The HBC contains two 8-bit bit-encoding pattern registers,
High-pattern (HPATTERN) and Low-pattern (LPATTERN). The
encoding pattern stored in the HPATTERN register is transmit-
ted when the data bit value to be encoded is a 1. Similarly, the
pattern stored in the LPATTERN register is transmitted when the
data bit value to be encoded is a 0. The HBC transmits each
encoded pattern MSB first.
The number of bits transmitted from the HPATTERN and LPAT-
TERN registers is software programmable through the Bit
Period Configuration (BPSEL) register (see Figure 22). During
the transmission of HPATTERN, the number of bits transmitted
is configured by BPH[2:0] (BPSEL[2:0]) while BPL[2:0]
(BPSEL[5:3]) configures the number of transmitted bits for the
LPATTERN. The HBC allows from 2 (0x1) to 8 (0x7) encoding
pattern bits to be transmitted from each register. Upon a reset,
BPSEL is initially 0 disabling the HBC from transmitting pattern
bits from either register.
The Data (DAT0) register is used to store up to 8 bits of data to
be encoded and transmitted by the HBC. This data is shifted, bit
by bit, MSB to LSB into a 1-bit decision register. If the active bit
shifted into the decision register is 1, the pattern in the HPAT-
TERN register is shifted out of the output port. Similarly, if the
active bit is 0 the pattern in the LPATTERN register is shifted
out.
The HBC control (HBCNTRL) register is used to configure and
control the data transmission. HBCNTRL is divided in 5 different
controlling signal FRAME[2:0], IOSEL, TXBUSY, START /
STOP, and OCFLAG (see Figure 23.)
FRAME[2:0] selects the number of bits of DAT0 to encode and
transmit. The HBC allows from 2 (0x1) to 8 (0x7) DAT0 bits to be
encoded and transmitted. Upon a reset, FRAME is initialized to
zero disabling the DAT0’s decision register transmitting no data.
The IOSEL signal selects the transmission to output (TX)
through either port G2 or G5. If IOSEL is 1, G5 is selected as
the output port otherwise G2 is selected.
The TXBUSY signal is read only and is used to inform software
that a transmission is in progress. TXBUSY goes high when the
encoded data begins to shift out of the output port and will
remains high during each consecutive DAT0 frame bit transmis-
sion (see Figure 25). The HBC will clear the TXBUSY signal
when the last DAT0 encoded bit of the frame is transmitted and
the STOP signal is 0.
The START / STOP signal controls the encoding and transmis-
sion process for each data frame. When software sets the
START / STOP bit the DAT0 frame transmission process begins.
The START signal will remain high until the beginning of the last
encoded DAT0 frame bit transmission. The HBC then clears the
START / STOP bit allowing software to elect to either continue
with a new DAT0 frame transmission or stop the transmission all
together (see Figure 25). If TXBUSY is 0 when the START sig-
nal is enabled, a synchronization period occurs before any data
is transmitted lasting the amount of time to transmit a 0 encoded
bit (see Figure 24).
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ACE1502 Product Family Rev. 1.7
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