ACE1502 Datasheet, PDF (28/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

Figure 36. Recommended HALT Flow
Normal Mode
Multi-Input
Wakeup
LD HALT, #01H
HALT Mode
LD PMC, #00H
Resume Normal
Mode
16. IDLE Mode
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed
into IDLE mode by setting the IDLE enable bit (EIDLE) of the
HALT register through software using only the “LD M, #” instruc-
tion. EIDLE is a write only bit and is automatically cleared upon
exiting IDLE. The IDLE mode operation is similar to HALT
except the internal oscillator, the Watchdog, and the Timer 0
remain active while the other on-chip systems including the LBD
and the BOR circuits are shut down.
The device automatically wakes from IDLE mode by the Timer 0
overflow every 8192 cycles (see Section 5). Before entering
IDLE mode, software must clear the WKEN register to disable
the MIW block. Once a wake from IDLE mode is triggered, the
core will begin normal operation by the next clock cycle. Imme-
diately after exiting IDLE mode, software must clear the Power
Mode Clear (PMC) register by using only the “LD M, #” instruc-
tion. (See Figure 37.)
Figure 37. Recommended IDLE Flow
Timer0
Underflow
Multi-Input
Wakeup
Normal Mode
LD HALT, #02H
IDLE Mode
LD PMC, #00H
Resume Normal
Mode
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ACE1502 Product Family Rev. 1.7
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