ACE1502 Datasheet, PDF (19/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

The OCFLAG signal is read only and goes high when the last
encoded bit of the DAT0 frame is transmitting. The OCFLAG sig-
nal is used to inform software that the DAT0 frame transmission
operation is completing (see Figure 25). If multiple DAT0 frames
are to be transmitted consecutively, software should poll the
OCFLAG signal for a 1. Once OCFLAG is 1, DAT0 must be
reload and the START / STOP bit must be restored to 1 in order
to begin the new frame transmission without interruptions (the
synchronization period). Since OCFLAG remains high during
the entire last encoded DAT0 frame bit transmission, software
should wait for the HBC to clear the OCFLAG signal before poll-
ing for the new OCFLAG high pulse. If new data is not reloaded
into DAT0 and the START signal (STOP is active) is not set
before the OCFLAG is 0, the transmission process will end
(TXBUSY is cleared) and a new process will begin starting with
the synchronization period.
Figure 24 and Figure 25 shows how the HBC performs its data
encoding. In the example, two frames are encoded and trans-
mitted consecutively with the following bit encoding format spec-
ification:
1. Transmission frequency = 62.5KHz
2. Data to be encoded = 0x52, 0x92 (all 8-bits)
3. Each bit should be encoded as a 3-bit binary value,
‘1’ = 110b and ‘0’ = 100b
4. Transmission output port : G2
To perform the data transmission, software must first initialize
the PSCALE, BPSEL, HPATTERN, LPATTERN, and DAT0
registers with the appropriate values.
LD PSCALE, #03H
LD BPSEL, #012H
LD HPATTERN, #0C0H
LD LPATTERN, #090H
LD DAT0, #052H
; (1MHz ?? 4) ?? 4 = 62.5KHz
; BPH = 2, BPL = 2 (3 bits each)
; HPATTERN = 0xC0
; LPATTERN = 0x90
; DAT0 = 0x52
Once the basic registers are initialized, the HBC can be started.
(At the same time, software must set the number of data bits per
data frame and select the desired output port.)
LD HBCNTRL, #27H
; START / STOP = 1,
FRAME = 7, IOSEL = 0
After the HBC has started, software must then poll the OCFLAG
for a high pulse and restore the DAT0 register and the START
signal to continue with the next data transmission.
LOOP_HI:
IFBIT OCFLAG, HBCNTRL
JP NXT_FRAME
JP LOOP_HI
; Wait for OCFLAG = 1
NXT_FRAME:
LD DAT0, #092H
SBIT START, HBCNTRL
; DAT0 = 0x92
; START / STOP = 1
If software is to proceed with another data transmission, the
OCFLAG must be zero before polling for the next OCFLAG high
pulse. However, since the specification in the example requires
no other data transmission software can proceed as desired.
LOOP_LO:
IFBIT OCFLAG, HBCNTRL
JP LOOP_LO
Etc.
; Wait for OCFLAG = 0
; Program proceeds
as desired
Figure 21. Hardware Bit-coder (HBC) Block Diagram
IR/RF
CLOCK
CPU
CLOCK
Fixed
Clock Divider
by 4
PSCALE
8
[PSCALE]
RFCLK
StopShift
HPATTERN
b7
A
Y
G2
B
RFCLK
StopShift
LPATTERN
b7
G5
IOSEL
HBCNTRL[6]
Down
Counter
ShiftCLK
DAT0 ^b7
NoShift OCFLAG
3
Y
A
B
3
FRAME[2:0]
[HBCNTRL]
OCFLAG
HBCNTRL[7]
3
3
BPH[2:0]
[BPSEL]
BPL[2:0]
[BPSEL]
Sync
LOGIC
START/STOP
HBCNTRL[5]
TXBUSY
HBCNTRL[4]
19
ACE1502 Product Family Rev. 1.7
www.fairchildsemi.com