ACE1502 Datasheet, PDF (12/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

3.4 Memory Map
All I/O ports, peripheral registers, and core registers (except the accumulator and the program counter) are mapped into the memory
space.
Table 10. Memory Mapped Registers
Address
Memory Space
Block
Contents
0x00 - 0x3F
0x40 - 0x7F
0x80-0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8-0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xC0
0xCE
0xCF
0xD0 - 0xFF
0x800 - 0xFF5
0xFF6 - 0xFF7
0xFF8 - 0xFF9
0xFFA - 0xFFB
0xFFC - 0xFFD
0xFFE - 0xFFF
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Program
Program
Program
Program
Program
Program
SRAM
EEPROM
Reserved
HBC
HBC
HBC
HBC
HBC
Timer1
Timer1
HBC
Timer1
Timer1
Timer1
Timer1
Timer1
MIW
MIW
MIW
I/O
I/O
I/O
Timer0
Timer0
Clock
Reserved
Init. Register
Init. Register
LBD
Core
Core
Clock
Core
Core
Reserved
EEPROM
Core
Core
Core
Core
Reserved
Data RAM
Data EEPROM
HBCNTRL register
PSCALE register
HPATTERN register
LPATTERN register
BPSEL register
T1RBLO register
T1RBHI register
DAT0 register
T1RALO register
T1RAHI register
TMR1LO register
TMR1HI register
T1CNTRL register
WKEDG register
WKPND register
WKEN register
PORTGD register
PORTGC register
PORTGP register
WDSVR register
T0CNTRL register
HALT mode register
Initialization Register 1
Initialization Register 2
LBD register
XHI register
XLO register
Power Mode Clear (PMC) Register
SP register
Status register (SR)
Code EEPROM
Timer0 Interrupt vector
Timer1 Interrupt vector
MIW Interrupt vector
Soft Interrupt vector
12
ACE1502 Product Family Rev. 1.7
www.fairchildsemi.com