ACE1502 Datasheet, PDF (27/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

12. RESET block
When a RESET sequence is initiated, all I/O registers will be
reset setting all I/Os to high-impedence inputs. The system
clock is restarted after the required clock start-up delay. A reset
is generated by any one of the following four conditions:
13. Power-On Reset
The Power-On Reset (POR) circuit is guaranteed to work if the
rate of rise of Vcc is no slower than 10ms/1volt. The POR circuit
was designed to respond to fast low to high transitions between
0V and Vcc. The circuit will not work if Vcc does not drop to 0V
before the next power-up sequence. In applications where 1)
the Vcc rise is slower than 10ms/1 volt or 2) Vcc does not drop
14. CLOCK
The ACEx microcontroller has an on-board oscillator trimmed to
a frequency of 2MHz who is divided down by two yielding a
1MHz frequency. (See AC Electrical Characteristics) Upon
power-up, the on-chip oscillator runs continuously unless enter-
ing HALT mode or using an external clock source.
If required, an external oscillator circuit may be used depending
on the states of the CMODE bits of the initialization register.
(See Table 16) When the device is driven using an external
clock, the clock input to the device (G1/CKI) can range between
DC to 4MHz. For external crystal configuration, the output clock
(CKO) is on the G0 pin. (See Figure 34.) If the device is config-
ured for an external square clock, it will not be divided.
Table 16. CMODEx Bit Definition
CMODE [1] CMODE [0]
0
0
0
1
1
0
1
1
Clock Type
Internal 1 MHz clock
External square clock
External crystal/resonator
Reserved
15. HALT Mode
The HALT mode is a power saving feature that almost com-
pletely shuts down the device for current conservation. The
device is placed into HALT mode by setting the HALT enable bit
(EHALT) of the HALT register through software using only the
“LD M, #” instruction. EHALT is a write only bit and is automati-
cally cleared upon exiting HALT. When entering HALT, the inter-
nal oscillator and all the on-chip systems including the LBD and
the BOR circuits are shut down.
Figure 35. HALT Register Definition
Bit 7
Undefined
Bit 6
undefined
Bit 5
undefined
Bit 4
undefined
• Power-on Reset (as described in Section 13)
• Brown-out Reset (as described in Section 11.1)
• Watchdog Reset (as described in Section 6)
• External Reset ¹⁸ (as described in Section 13)
18. Available only on the 14-pin package option
to 0V before the next power-up sequence the external reset
option should be used.
The external reset provides a way to properly reset the ACEx
microcontroller if POR cannot be used in the application. The
external reset pin contains an internal pull-up resistor. There-
fore, to reset the device the reset pin should be held low for at
least 2ms so that the internal clock has enough time to stabilize.
Figure 34. Crystal
CKI
CKO
R2
R1
C2
C1
The device can exit HALT mode only by the MIW circuit. There-
fore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 8) After a wakeup from
HALT, a 1ms start-up delay is initiated to allow the internal oscil-
lator to stabilize before normal execution resumes. Immediately
after exiting HALT, software must clear the Power Mode Clear
(PMC) register by only using the “LD M, #” instruction. (See Fig-
ure 36)
Bit 3
undefined
Bit 2
undefined
Bit 1
EIDLE
Bit 0
EHALT
27
ACE1502 Product Family Rev. 1.7
www.fairchildsemi.com