ACE1502 Datasheet, PDF (14/33 Pages) Fairchild Semiconductor – Arithmetic Controller Engine for Low Power Applications

Table 11. Timer 1 Control Register (T1CNTRL)
T1CNTRL Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
T1C3
T1C2
T1C1
T1C0
T1PND
T1EN
M1S1
T1RBEN
Function
Timer TIMER1 control bit 3 (see Table 12)
Timer TIMER1 control bit 2 (see Table 12)
Timer TIMER1 control bit 1 (see Table 12)
Timer TIMER1 run: 1= Start timer, 0 = Stop timer;
or Timer TIMER1 underflow interrrupt pending flag in input capture mode
Timer1 interrupt pending flag: 1 = Timer1 interrupt
Pending, 0 = Timer1 interrupt not pending
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Capture type: 0 = Pulse capture, 1 = Cycle capture (see Table 12)
PWM Mode: 0 = Timer1 reload on T1RA, 1 = TIMER1 reload on T1RA and T1RB
(always starting with T1RA)
Table 12. Timer 1 Operating Modes
T1 T1 T1 M4 T1
C3 C2 C1 S1 RB Timer Mode Source
Interrupt
0
0
0
X
X MODE 2
TIMER1 Underflow
0
0
1
X
X MODE 2
TIMER1 Underflow
1
0
1
X
0 MODE 1 T1 Toggle
Autoreload T1RA
1
0
0
X
0 MODE 1 No T1 Toggle
Autoreload T1RA
1
0
1
X
1 MODE 1 T1 Toggle
Autoreload T1RA/T1RB
1
0
0
X
1 MODE 1 No T1 Toggle
Autoreload T1RA/T1RB
0
1
0
X
X MODE 3 Captures:
T1 Pos Edge
Pos. T1 Edge
0
1
1
X
X MODE 3 Captures:
T1 Neg Edge
Neg. T1 Edge
1
1
0
0
X MODE 4
Pos. to Neg.
1
1
0
1
X MODE 4
Pos. to Pos.
1
1
1
0
X MODE 4
Neg. to Pos.
1
1
1
1
X MODE 4
Neg. to Neg.
Timer Counts-on
T1 Pos. Edge
T1 Neg. Edge
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
Instruction Clock
4.2 Mode 1: Pulse Width Modulation (PWM) Mode
In the PWM mode, the timer counts down at the instruction
clock rate. When an underflow occurs, the timer register is
reloaded from T1RA/T1RB and the count down proceeds from
the loaded value. At every underflow, a pending flag (T1PND)
located in the T1CNTRL register is set. Software must then
clear the T1PND flag and load the T1RA/T1RB register with an
alternate PWM value (if desired.) In addition, the timer can be
configured to toggle the T1 output bit upon underflow. Configur-
ing the timer to toggle T1 results in the generation of a signal
outputted from port G2 with the width and duty cycle controlled
by the values stored in the T1RA/T1RB. A block diagram of the
timer’s PWM mode of operation is shown in Figure 15.
The PWM timer can be configured to use the T1RA register only
for auto-reloading the timer registers or can be configured to
use both T1RA and T1RB alternately. If the T1RBEN bit of the
T1CNTRL register is 0, the PWM timer will reload using only
T1RA ignoring any value store in the T1RB register. However, if
the T1RBEN bit is 1 the PWM timer will be reloaded using both
the T1RA and T1RB registers. A hardware select logic is imple-
mented to select between T1RA and T1RB alternately, always
starting with T1RA, every timer underflows to auto-reload the
timer registers. This feature is useful when a signal with variable
duty cycle needs to be generated without software intervention.
The timer has one interrupt (TMRI1) that is maskable through
the T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable)
bit of the SR is set. If interrupts are enabled, the timer will gen-
erate an interrupt each time T1PND flags is set (whenever the
timer underflows provided that the pending flag was cleared.)
The interrupt service routine is responsible for proper handling
of the T1PND flag and the T1EN bit.
The interrupt will be synchronous with every rising and falling
edge of the T1 output signal. Generating interrupts only on ris-
ing or falling edges of T1 is achievable through appropriate han-
dling of the T1EN bit or T1PND flag through software.
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ACE1502 Product Family Rev. 1.7
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