XRT75R12 Datasheet, PDF (86/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
ADDRESS
LOCATION
0
1
2
3
4
5
6
7
89 A
B
C DE F
0x7-
0x8- ^APST IER6 ISR6 AS6 TC6 RC6 CC6 JA6 ^APSR
EM6 EL6 EH6
0X9-
IER7 ISR7 AS7 TC7 RC7 CC7 JA7
EM7 EL7 EH7
0xA-
IER8 ISR8 AS8 TC8 RC8 CC8 JA8
EM8 EL8 EH8
0xB-
IER9 ISR9 AS9 TC9 RC9 CC9 JA9
EM9 EL9 EH9
0xC-
IER10 ISR10 AS10 TC10 RC10 CC10 JA10
EM10 EL10 EH10
0xD-
IER11 ISR11 AS11 TC11 RC11 CC11 JA11
EM11 EL11 EH11
0xE- ^CIE CIS
0xF-
TABLE 45: ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC
BIT 7
Msb
R/W
BIT 6
R/W
BIT 5
R/W
BIT 4
R/W
BIT 3
R/W
BIT 2
R/W
BIT 1
R/W
BIT 0
Ls bit
R/W
Each channel contains a dedicated 16 bit PRBS error counter. When enabled this counter will accumulate
PRBS errors (as well as excess zeros and LCVs). The LS byte will "carry" a one over to the MS byte each time
it rolls over from 255 to zero until the MS byte also reaches 255. When both counters reach 255, no further
errors will be accumulated and "all ones" will signify an overflow condition.
The counter can be read while in the active count mode. Either register may be read "on the fly" and the other
byte will be simultaneously transferred into the channel’s Error Holding register. The holding register may then
be read to supply the Host with a correct 16 bit count (as of the instant of reading). With this mechanism, the
Host could rapidly cycle thru reading all twelve counters in order (storing the read byte in scratch RAM) and
then come back and read the second byte from each holding register to form the 16 bit accumulation in the
Host system.
83