XRT75R12 Datasheet, PDF (65/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12
REV. P1.0.2
TABLE 21: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR224 (ADDRESS LOCATION = 0XE0)
BIT 7
Reserved
BIT 6
Reserved
BIT 5
Channel 11
Interrupt
Enable
R/W
BIT 4
Channel 10
Interrupt
Enable
R/W
BIT 3
Channel 9
Interrupt
Enable
R/W
BIT 2
Channel 8
Interrupt
Enable
R/W
BIT 1
Channel 7
Interrupt
Enable
R/W
BIT 0
Channel 6
Interrupt
Enable
R/W
BIT
NUMBER
7,6
5
4
3
2
1
0
NAME
Reserved
Channel 11 Interrupt Enable
Channel 10 Interrupt Enable
Channel 9 Interrupt Enable
Channel 8 Interrupt Enable
Channel 7 Interrupt Enable
Channel 6 Interrupt Enable
TYPE
DESCRIPTION
R/W Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
• To enable Channel n for Interrupt Generation at the Channel
Level
• To disable all Interrupts associated with Channel n within the
XRT75R12
This is a "master" enable bit for each channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to
the Host via the INT pin.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved Reserved Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
Channel 0
Interrupt Status Interrupt Status Interrupt Status Interrupt Status Interrupt Status Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
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