XRT75R12 Datasheet, PDF (77/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12
REV. P1.0.2
TABLE 32: XRT75R12 REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_N)
TABLE 33: TRANSMIT CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM4
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Reserved
Internal Insert PRBS
Transmit
Error
Drive Monitor
Reserved
TAOS
TxCLKINV
R/W
R/W
R/W
R/W
BIT 0
TxLEV
R/W
BIT NUMBER
7-6
5
NAME
Reserved
Internal Transmit
Drive Monitor
Enable
4
Insert PRBS Error
3
Reserved
TYPE
DESCRIPTION
R/W Internal Transmit Drive Monitor Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Transmit Section of
Channel_n to either internally or externally monitor the TTIP_n and
TRING_n output pins for bipolar pulses, in order to determine whether
to declare the Transmit DMO Alarm condition.
If the user configures the Transmit Section to externally monitor the
TTIP_n and TRING_n output pins (for bipolar pulses) then the user
must connect the MTIP_n and MRING_n input pins to their corre-
sponding TTIP_n and TRING_n output pins (via a 270 ohm series
resistor).
If the user configures the Transmit Section to internally monitor the
TTIP_n and TRING_n output pins (for bipolar pulses), the user does
NOT need to conect the MTIP_n and MRING_n input pins. This moni-
toring will be performed internally at the TTIP_n and TRING_n pads.
0 - Configures the Transmit Drive Monitor to externally monitor the
TTIP_n and TRING_n output pins for bipolar pulses.
1 - Configures the Transmit Drive Monitor to internally monitor the
TTIP_n and TRING_n output pins for bipolar pulses.
R/W Insert PRBS Error - Channel_n:
A "0 to 1" transition within this bit-field causes the PRBS Generator
(within the Transmit Section of Channel_n) to generate a single bit
error within the outbound PRBS pattern-stream.
NOTES:
1. This bit-field is only active if the PRBS Generator and
Receiver have been enabled within the corresponding
Channel.
2. After writing the "1" into this register, the user must execute a
write operation to clear this particular register bit to "0" in
order to facilitate the next "0 to 1" transition in this bit-field.
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