XRT75R12 Datasheet, PDF (84/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
BIT NUMBER
NAME
TYPE
DESCRIPTION
1
JA in Tx Path Ch_n R/W Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin is used to configure the Jitter Attenuator (within
Channel_n) to operate in either the Transmit or Receive path, as
described below.
0 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Receive Path.
1 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Transmit Path.
0
JA0 Ch_n
R/W Jitter Attenuator Configuration Select Input - Bit 0:
See the description for Bit 2 (JA1 Ch_n).
TABLE 40: XRT75R12 REGISTER MAP SHOWING ERROR COUNTER MSBYTE REGISTERS (EM_N)
ADDRESS
LOCATION
0
1
2
3
4
5
6
7
89 A
B
C DE F
0x0- ^APST IER0 ISR0 AS0 TC0 RC0 CC0 JA0 ^APSR
EM0 EL0 EH0
0X1-
IER1 ISR1 AS1 TC1 RC1 CC1 JA1
EM1 EL1 EH1
0x2-
IER2 ISR2 AS2 TC2 RC2 CC2 JA2
EM2 EL2 EH2
0x3-
IER3 ISR3 AS3 TC3 RC3 CC3 JA3
EM3 EL3 EH3
0x4-
IER4 ISR4 AS4 TC4 RC4 CC4 JA4
EM4 EL4 EH4
0x5-
IER5 ISR5 AS5 TC5 RC5 CC5 JA5
EM5 EL5 EH5
0x6-
CIE _CIS
PN VN
0x7-
0x8- ^APST IER6 ISR6 AS6 TC6 RC6 CC6 JA6 ^APSR
EM6 EL6 EH6
0X9-
IER7 ISR7 AS7 TC7 RC7 CC7 JA7
EM7 EL7 EH7
0xA-
IER8 ISR8 AS8 TC8 RC8 CC8 JA8
EM8 EL8 EH8
0xB-
IER9 ISR9 AS9 TC9 RC9 CC9 JA9
EM9 EL9 EH9
0xC-
IER10 ISR10 AS10 TC10 RC10 CC10 JA10
EM10 EL10 EH10
0xD-
IER11 ISR11 AS11 TC11 RC11 CC11 JA11
EM11 EL11 EH11
0xE- ^CIE CIS
0xF-
TABLE 41: ERROR COUNTER MSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMA
BIT 7
Msb
R/W
BIT 6
R/W
BIT 5
R/W
BIT 4
R/W
BIT 3
R/W
BIT 2
R/W
BIT 1
R/W
BIT 0
9th bit
R/W
81