XRT75R12 Datasheet, PDF (83/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12
REV. P1.0.2
TABLE 38: XRT75R12 REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_N)
TABLE39:JITTER ATTENUATORCONTROLREGISTER-CHANNELNADDRESSLOCATION=0XM7
BIT 7
BIT 6
BIT 5
Reserved
BIT 4
BIT 3
JA RESET
Ch_n
R/W
BIT 2
JA1 Ch_n
R/W
BIT 1
JA in Tx Path
Ch_n
R/W
BIT 0
JA0 Ch_n
R/W
BIT NUMBER
7-4
3
NAME
Reserved
JA RESET Ch_n
2
JA1 Ch_n
TYPE
DESCRIPTION
R/W Jitter Attenuator RESET - Channel_n:
Writing a "0 to 1" transition within this bit-field will configure the Jitter
Attenuator (within Channel_n) to execute a RESET operation.
Whenever the user executes a RESET operation, then following will
occur.
• The READ and WRITE pointers (within the Jitter Attenuator FIFO)
will be reset to their default values.
• The contents of the Jitter Attenuator FIFO will be flushed.
NOTE: The user must follow up any "0 to 1" transition with the
appropriate write operate to set this bit-field back to "0", in
order to resume normal operation with the Jitter Attenuator.
R/W Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is used to do
any of the following.
• To enable or disable the Jitter Attenuator corresponding to
Channel_n.
• To select the FIFO Depth for the Jitter Attenuator within Channel_n.
The relationship between the settings of these two bit-fields and the
Enable/Disable States, and FIFO Depths is presented below.
JA0 JA1
0
0
0
1
1
0
1
1
Jitter Attenuator Mode
FIFO Depth = 16 bits
FIFO Depth = 32 bits
Disabled
Disabled
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