XRT75R12 Datasheet, PDF (73/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12
REV. P1.0.2
TABLE 30: XRT75R12 REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_N)
TABLE 31: ALARM STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM3
BIT 7
Reserved
BIT 6
BIT 5
Loss of PRBS
Pattern Sync
Digital LOS
Defect
Declared
R/O
R/O
BIT 4
BIT 3
BIT 2
BIT 1
Analog LOS
Defect
Declared
FL
(FIFO Limit)
Alarm
Declared
Receive LOL Receive LOS
Defect
Defect
Declared
Declared
R/O
R/O
R/O
R/O
BIT 0
Transmit
DMO
Condition
R/O
BIT NUMBER
NAME
7
Reserved
6
Loss of PRBS Pat-
tern Lock
TYPE
DESCRIPTION
R/O Loss of PRBS Pattern Lock Indicator:
This READ-ONLY bit-field indicates whether or not the PRBS Receiver
(within the Receive Section of Channel n) is declaring PRBS Lock
within the incoming PRBS pattern.
If the PRBS Receiver detects a very large number of bit-errors within
its incoming data-stream, then it will declare the Loss of PRBS Lock
Condition.
Conversely, if the PRBS Receiver were to detect its pre-determined
PRBS pattern with the incoming DS3, E3 or STS-1 data-stream, (with
little or no bit errors) then the PRBS Receiver will clear the Loss of
PRBS Lock condition.
0 - Indicates that the PRBS Receiver is currently declaring the PRBS
Lock condition within the incoming DS3, E3 or STS-1 data-stream.
1 - Indicates that the PRBS Receiver is currently declaring the Loss of
PRBS Lock condition within the incoming DS3, E3 or STs-1 data-
stream.
NOTE: This register bit is only valid if all of the following are true.
a. The PRBS Generator block (within the Transmit Section of the
Chip is enabled).
b. The PRBS Receiver is enabled.
c. The PRBS Pattern (that is generated by the PRBS Generator) is
somehow looped back into the Receive Path (via the Line-Side)
and in-turn routed to the receive input of the PRBS Receiver.
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