XRT75R12 Datasheet, PDF (42/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 9: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
BIT RATE
(KB/S)
34368
44736
44736
51840
STANDARD
INPUT JITTER AMPLITUDE (UI _P-P)
A1
A2
A3
ITU-T G.823 1.5
0.15
-
GR-499
5
0.1
-
CORE Cat I
GR-499
10
0.3
-
CORE Cat II
GR-253
15
CORE Cat II
1.5
0.15
F1(HZ)
100
10
10
10
MODULATION FREQUENCY
F2(HZ) F3(KHZ) F4(KHZ) F5(KHZ)
1000
10
800
-
2.3k
60
300
-
669
22.3
300
-
30
300
2
20
5.2 JITTER TRANSFER
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as
the highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a
low bandwidth loop, typically using a voltage-controlled crystal oscillator (VCXO).
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter.
Table 10 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
TABLE 10: JITTER TRANSFER SPECIFICATION/REFERENCES
E3
ETSI TBR-24
DS3
GR-499 CORE section 7.3.2
Category I and Category II
STS-1
GR-253 CORE section 5.6.2.1
NOTE: The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
5.3 Jitter Attenuator
An advanced crystal-less jitter attenuator per channel is included in the XRT75R12. The jitter attenuator
requires no external crystal nor high-frequency reference clock. By clearing or setting the JATx/Rx_n bits in
the channel control registers selects the jitter attenuator either in the Receive or Transmit path on per channel
basis. The FIFO size can be either 16-bit or 32-bit. The bits JA0_n and JA1_n can be set to appropriate
combination to select the different FIFO sizes or to disable the Jitter Attenuator on a per channel basis. Data is
clocked into the FIFO with the associated clock signal (TxClk or RxClk) and clocked out of the FIFO with the
dejittered clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL_n
is set to “1” in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter. Table 11 specifies the jitter transfer mask requirements for various data rates:
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