XRT75R12 Datasheet, PDF (66/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
BIT
NUMBER
NAME
TYPE
DESCRIPTION
7, 6
Reserved
5
Channel 5 Interrupt Status R/O Channel n Interrupt Status Bit:
4
Channel 4 Interrupt Status
3
Channel 3 Interrupt Status
2
Channel 2 Interrupt Status
1
Channel 1 Interrupt Status
0
Channel 0 Interrupt Status
This READ-ONLY bit-field indicates whether the XRT75R12 has a
pending Channel n-related interrupt that is awaiting service. The
first six channels are serviced through this location and the other six
at address 0xE1. These two registers are used by the Host to iden-
tify the source channel of an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting
service.
1 - Indicates that there is at least one Channel n-related Interrupt
awaiting service. In this case, the user’s Interrupt Service routine
should be written such that the Microprocessor will now proceed to
read out the contents of the Source Level Interrupt Status Register -
Channel n (Address Locations = 0xn2) to determine the exact
source of the interrupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to
"0" until the user has read out the contents of the Source-
Level Interrupt Status Register bit, that corresponds to the
interrupt request channel.
TABLE 22: The above is: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61)
TABLE 23: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR225 (ADDRESS LOCATION = 0XE1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved Reserved Channel 11 Channel 10
Channel 9
Channel 8
Channel 7
Channel 6
Interrupt Status Interrupt Status Interrupt Status Interrupt Status Interrupt Status Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
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