XRT75R12 Datasheet, PDF (64/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
BIT
NUMBER
NAME
7,6
Reserved
5
TxON Ch 11
4
TxON Ch 10
3
TxON Ch 9
2
TxON Ch 8
1
TxON Ch 7
0
TxON Ch 6
TYPE
R/W
DESCRIPTION
Transmit Section ON - Channel n
This READ/WRITE bit-field is used to turn on or turn off the Transmit
Driver associated with Channel n on a per channel basis. If the user
turns on the Transmit Driver, then Channel n will transmit DS3, E3 or
STS-1 pulses on the line via the TTIP_n and TRING_ n output pins.
Conversely, if the user turns off the Transmit Driver (for channel n),
the TTIP_n and TRING_n output pins will be tri-stated.
0 - Shuts off the Transmit Driver associated with Channel n and tri-
states the TTIP_n and TRING_ n output pins.
1 - Turns on the Transmit Driver associated with Channel n.
NOTE: The master TxON control (pin # P4) must be in a high state
(logic 1) for this operation to turn on any channel.
TABLE 20: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR96 (ADDRESS LOCATION = 0X60)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Channel 5
Interrupt
Enable
Channel 4
Interrupt
Enable
Channel 3
Interrupt
Enable
Channel 2
Interrupt
Enable
Channel 1
Interrupt
Enable
Channel 0
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NUMBER
7,6
5
4
3
2
1
0
NAME
Unused
Channel 5 Interrupt Enable
Channel 4 Interrupt Enable
Channel 3 Interrupt Enable
Channel 2 Interrupt Enable
Channel 1 Interrupt Enable
Channel 0 Interrupt Enable
TYPE
DESCRIPTION
R/W Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
• To enable Channel n for Interrupt Generation at the Channel
Level
• To disable all Interrupts associated with Channel n within the
XRT75R12
This is a "master" enable bit for each channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to
the Host via the INT.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
61