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XRT75R12 Datasheet, PDF (52/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 36. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
PCLK
Addr[7:0]
CS
D[7:0]
RD
WR
RDY
READ OPERATION
t0
Valid Address
WRITE OPERATION
t0
Valid Address
Valid Data for Readback
t1
t2
Data Available to Write Into the LIU
t3
t4
TABLE 15: SYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL
t0
t1
t2
NA
t3
t4
NA
PARAMETER
Valid Address to CS Falling Edge
CS Falling Edge to RD Assert
RD Assert to RDY Assert
RD Pulse Width (t2)
CS Falling Edge to WR Assert
WR Assert to RDY Assert
WR Pulse Width (t4)
PCLK Period
PCLK Duty Cycle
PCLK "High/Low" time
MIN
0
MAX
-
UNITS
ns
0
-
ns
-
35
ns, see note 1
40
-
ns
0
-
ns
-
35
ns, see note 1
40
-
ns
15
ns
NOTE: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access
time, use the following formula: (PCLKperiod * 2) + 5ns
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