XR17V254_08 Datasheet, PDF (8/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.1
1.0 XR17V254 INTERNAL REGISTERS
The XR17V254 UART has three different sets of registers as shown in Figure 3. The PCI Local Bus
Configuration Space Registers are for plug-and-play auto-configuration when connecting the device to a the
PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI
local bus specification. The second register set is the Device Configuration Registers that are also
accessible directly from the PCI bus for programming general operating conditions of the device and
monitoring the status of various functions common to all four channels. These functions include all 4 channel
UARTs’ interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/
outputs control and status, sleep mode, soft-reset, and device identification and revision. And lastly, each
UART channel has its own set of internal UART Configuration Registers for its own operation control and
status reporting. All 4 sets of channel registers are embedded inside the device configuration registers space,
which provides faster access. The second and third set of registers are mapped into 2K of the PCI bus memory
address space. The following paragraphs describe all 3 sets of registers in detail.
FIGURE 3. THE XR17V254 REGISTER SETS
Device Configuration and
UART[7:0] Configuration
Registers are mapped on
to the Base Address
Register (BAR) in a 2K-
byte of memory address
space
PCI Local Bus
Interface
PCI Local Bus
Configuration Space
Registers for Plug-
and-Play Auto
Configuration
Vendor and Sub-vendor ID
and Product Model Number
in External EEPROM
Channel 0
INT, MPIO,
TIMER, REG
Channel 0
Channel 1
Channel 2
Channel 3
0x0000
0x0080
0x0200
0x0400
0x0600
0x07FF
Device Configuration Registers
4 channel Interrupts,
Multipurpose I/Os,
16-bit Timer/Counter,
Sleep, Reset, DVID, DREV
UART[3:0] Configuration
Registers
16550 Compatible and EXAR
Enhanced Registers
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, located at an address offset of
0x10 in the configuration space. Custom modification of certain registers is possible by using an external
93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of
information (see “Section 1.4, EEPROM Interface” on page 13) required by the auto-configuration setup.
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