XR17V254_08 Datasheet, PDF (19/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
REV. 1.0.1
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
TIMERCNTL [7:0] Register
The bits [3:0] of this register are used to issue commands. The commands are self-clearing, so reading this
register does not show the last written command. Reading this register returns a value of 0x01 when the Timer
interrupt is enabled and there is a pending Timer interrupt. It returns a value of 0x00 at all other times. The
default settings of the Timer, upon power-up, a hardware reset or upon the issue of a ’Timer Reset’ command
are:
■ Timer Interrupt Disabled
■ Re-triggerable mode selected
■ Internal crystal oscillator outputs selcted as clock source
■ Timer output not routed to MPIO[0]
■ Timer stopped
TABLE 10: TIMER CONTROL REGISTERS
TIMERCNTL [7:4] Reserved
TIMERCNTL [3:0]
These bits are used to invoke a series of commands that control the function of the Timer/Counter.
The commands 1100 to 1111 are reserved.
0001: Enable Timer Interrupt
0010: Disable Timer Interrupt
0011: Select One-shot mode
0100: Select Re-triggerable mode
0101: Select Internal Crystal Oscillator output as clock input for the Timer
0110: Select External Clock input through the TMRCK pin for the Timer
0111: Route Timer output to MPIO[0] pin
1000: De-route Timer output from MPIO[0]
1001: Start Timer
1010: Stop Timer
1011: Reset Timer
TIMER OPERATION
The following paragraphs describe the operation of the 16-bit Timer/Counter. The following conventions will be
used in this discussion:
■ ’N’ is the 16-bit value programmed in the TIMER MSB, LSB registers
■ P +Q = N, where ’P’ and ’Q’ are approximately half of ’N’.
■ If N is even, P = Q = N/2.
■ If N is odd, P = (N – 1)/2 and Q = (N + 1)/2.
■ ‘N’ can take any value from 0x0002 to 0xFFFF.
Timer Operation in One-Shot Mode:
In the one-shot mode, the Timer output will stay HIGH when started (default state) and will continue to stay
HIGH until it times out (reaches the terminal count of ‘N’ clocks), at which time it will become LOW and stay
LOW. If the Timer is re-started before the Timer times out, the counter is reset and the Timer will wait for
another time-out period before setting its output LOW (See Figure 7). If the Timer times out, re-starting the
Timer does not have any effect and a ’Stop Timer’ command needs to be issued first which will set the Timer
output to its default HIGH state. The Timer must be programmed while it is stopped since the following
operations are blocked after the Timer has been started:
■ Any write to TIMER MSB, LSB registers
■ Issue of any command other than ’Start Timer’, ’Stop Timer’ and ’Reset Timer’
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