XR17V254_08 Datasheet, PDF (37/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
REV. 1.0.1
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
TABLE 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS ^REG
A3-A0 ^NAME
READ/
WRITE
BIT [7]
BIT [6]
BIT [5]
BIT [4]
BIT [3] BIT [2] BIT[1] BIT [0] COMMENT
1001
EFR
R/W Auto Auto Special Enable Soft-
CTS/
DSR
Enable
RTS/
DTR
Enable
Char
Select
IER [7:5],
ISR [5:4],
FCR[5:4],
ware
Flow
Cntl
MCR[7:5,2] ^{Bit [3]}
MSR[7:4]
Soft-
ware
Flow
Cntl
Bit [2]
Soft-
ware
Flow
Cntl
Bit [1]
Soft-
ware
Flow
Cntl
Bit [0]
1 0 1 0 TXCNT R Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]
1 0 1 0 TXTRG W Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]
1 0 1 1 RXCNT R Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]
1 0 1 1 RXTRG W Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]
1 1 0 0 XCHAR R
0
0
0
0
TX Xon TX Xoff Xon Det. Xoff Det. Self clear
Indicator Indicator Indicator Indicator after read
1 1 0 0 XOFF1 W Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit-2 Bit [1] Bit [0]
1 1 0 1 XOFF2 W Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit-2 Bit [1] Bit [0]
1 1 1 0 XON1 W Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit-2 Bit [1] Bit [0]
1 1 1 1 XON2 W Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit-2 Bit [1] Bit [0]
NOTE: MCR bits [3:2] (OP1 and OP2 outputs) are not available in the XR17V254. They are present for 16C550
compatibility during Internal loopback, see Figure 14.
4.6 Transmitter
The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit [0]. TSR shifts out every data bit with the 16X or 8X
internal clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of
data bits, inserts the proper parity bit if enabled, and adds the stop bit(s). The status of the THR and TSR are
reported in the Line Status Register (LSR bit [6:5]).
4.6.1 Transmit Holding Register (THR)
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (bit [0]) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit[0]. A THR empty
interrupt can be generated when it is enabled in IER bit [1].
4.6.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit [5]) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit [1]) when it is
enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
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