XR17V254_08 Datasheet, PDF (23/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
REV. 1.0.1
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
REGB [23:16] (default 0x00)
REGB register provides a control for simultaneous write to all 4 UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data in an external EEPROM.
1.6.8 REGB Register
REGB[16](Read/Write)
REGB[19:17]
REGB[20] (Write-Only)
REGB[21] (Write-Only)
REGB[22] (Write-Only)
REGB[23] (Read-Only)
LOW (default) write to each UART configuration registers individually.
HIGH enables simultaneous write to all 4 UARTs configuration register.
Reserved
Control the EECK, clock, output (pin 116) on the EEPROM interface.
Control the EECS, chips select, output (pin 115) to the EEPROM device.
EEDI (pin 114) data input. Write data to the EEPROM device.
EEDO (pin 113) data output. Read data from the EEPROM device.
1.6.9 Multi-Purpose Inputs and Outputs
The V254 provides 8 multi-purpose inputs/outputs MPIO[7:0] for general use. Each pin can be programmed to
be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to
generate an interrupt. The outputs can be set to be normal HIGH or LOW state, or 3-state. Their functions and
definitions are programmed through 5 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV and MPIOSEL. If all
8 pins are set for inputs, all 8 interrupts would be Or’ed together. The Or’ed interrupt is reported in the channel
0 UART interrupt status, see Interrupt Status Register. The pins may also be programmed to be outputs and to
the 3-state condition for signal sharing. The MPIO[0] pin can be programmed to show the Timer output. When
it is programmed to be the Timer output, all the above 5 registers lose control over the MPIO[0] pin. For details
on Timer output, please see “Section 1.6.2, General Purpose 16-bit Timer/Counter [TIMERMSB,
TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-00-00)” on page 18.
1.6.10 MPIO REGISTER
Bit [7] represents MPIO7 pin and bit [0] represents MPIO0 pin. There are 5 registers that select, control and
monitor the 8 multipurpose inputs and outputs. Figure 9 shows the internal circuitry.
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