XR17V254_08 Datasheet, PDF (62/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.1
FIGURE 21. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND TRANSMIT DATA BURST WRITE OPERA-
TION
CLK
Host
1
2
3
4
5
6
7
8
9
FRAME#
Host
AD[31:0]
Host
Target
Address
Data
DWORD
Data
Data
Data
DWORD DWORD DWORD
Data DWORD
C/BE[3:0]#
Host
Bus
CMD
Byte Enable# = DWORD
IRDY#
Host
10
11
TRDY#
Target
DEVSEL#
Target
PAR
Host
Target
Address
Parity
Data
Parity
Data
Parity
Data
Parity
Data
Parity
PERR#
Target
Active Active Active Active
SERR#
Target
Active
Note: PERR# and SERR are optional in a bus target application.
Even Parity is on AD[31:0], C/BE[3:0]#, and PAR
Data
Parity
Active
PCI BWR
62