XR17V254_08 Datasheet, PDF (10/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
REV. 1.0.1
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
0x24 31:0
RO Unimplemented Base Address Register (returns zeros)
0x00000000
0x28 31:0
RO Reserved
0x00000000
0x2C 31:16
EWR Subsystem ID (write from external EEPROM by customer)
0x0000
15:0
EWR Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
0x0000
0x30 31:0
RO Expansion ROM Base Address (Unimplemented)
0x00000000
0x34 31:8
RO Reserved (returns zeros)
0x000000
7:0
RO Capability Pointer (Implemented for Power Management)
0x40
0x38 31:0
RO Reserved (returns zeros)
0x00000000
0x3C 31:24
RO Unimplemented MAXLAT
0x00
23:16
RO Unimplemented MINGNT
0x00
15:8
RO Interrupt Pin, use INTA#.
0x01
7:0
RWR Interrupt Line.
0xXX
NOTE: EWR=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. RWC=Read/Write-
Clear.
1.2 Power Management Registers
The Power Management Registers are implemented in 2 DWORDs starting at address offset 0x40 of the PCI
local bus configuration space. The bit definitions of these registers are shown in Table 2 below. The V254
complies with Revision 1.1 of the PCI Power Management Interface Specification.
ADDRESS
OFFSET
0x40
0x44
TABLE 2: POWER MANAGEMENT REGISTERS
BITS
TYPE
DESCRIPTION
31:16 See Below
31:27
RO
26:20
RO
19
RO
18:16
RO
15:8
RO
7:0
RO
31:24
RO
23:16
RO
15:0 See Below
15
RWC
Power Management Capabilities (PMC)
PME Support (PME# can be asserted from D3_hot only)
Reserved or Not Supported
PME Clock (PCI clock is required for PME# generation)
Version
Next Item Pointer
Capability ID
Unimplemented Data Register
Unimplemented Bridge Support Extensions
Power Management Control/Status Register (PMCSR)
PME_Status
RESET VALUE
(HEX OR BINARY)
See Below
01000b
0000000b
1b
010b
0x00
0x01
0x00
0x00
See Below
0b
10