XR17V254_08 Datasheet, PDF (40/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
4.7.2 Receiver Operation with FIFO
FIGURE 18. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
REV. 1.0.1
16X or 8X Sampling
Clock (8XMODE Reg.)
64 bytes by 11-
bit wide FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Receive Data
FIFO
(64-byte)
Data falls to 40 ^{RTS#/DTR# re-asserts when data falls below}
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
FIFO Trigger=48 ^{RHR Interrupt (ISR bit-2) is programmed}
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
Receive
Data
Data fills to 56 ^{RTS#/DTR# de-asserts when data fills above}
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RXFIFO1
5.0 UART CONFIGURATION REGISTERS
5.1 Receive Holding Register (RHR) - Read only
SEE”RECEIVER” ON PAGE 39.
5.2 Transmit Holding Register (THR) - Write only
SEE”TRANSMITTER” ON PAGE 37.
5.3 Baud Rate Generator Divisors (DLM, DLL and DLD)
The Baud Rate Generator (BRG) generates the data rate for the transmitter and receiver. The rate is
programmed through registers DLM, DLL and DLD which are only accessible when LCR bit [7] is set to logic 1.
Refer to “Section 4.1, Programmable Baud Rate Generator with Fractional Divisor” on page 29 for more
details.
5.4 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
5.4.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR bit [0] = a logic 1) and receive interrupts (IER bit [0] = logic 1) are enabled, the
RHR interrupts (see ISR bits [4:3]) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR bit [0]) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
40