XR17V254_08 Datasheet, PDF (13/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
REV. 1.0.1
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
1.4 EEPROM Interface
The V254 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The
EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided
in order to program the registers in the PCI Configuration Space of the PCI UART during power-up. The
following table gives the mapping of the EEPROM memory to the registers in the V254’s PCI Configuration
Space. When the PCI RST# is negated, the V254 will download the data from the EEPROM, if it detects a
HIGH on the EECS pin. The V254 takes a maximum of 2¹⁶ PCI clocks from the rising edge of the PCI RST#
signal to read the EEPROM data. For more details on the EEPROM interface, please refer to the application
note DAN112 on Exar’s website.
TABLE 4: EEPROM ADDRESS DEFINITIONS
EEPROM MEMORY
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
EEPROM DATA [D15:D0]
Vendor ID
Device ID
Class Code^*
Class Code (Continued)
Subsystem Vendor ID
Subsystem ID
Special Register (Lower Word)
Special Register (Upper Word)
V254’S PCI CONFIGURATION
SPACE ADDRESS
(WORD OFFSET)
0x00
0x02
0x08
0x0A
0x2C
0x2E
0x48
0x4A
DEFAULT VALUES
0x13A8
0x0254
0x0200
0x0700
0x0000
0x0000
0x0000
0x0000
NOTE: * Only the upper 8 bits in this word in EEPROM location are used and the lower 8 bits are ignored. The lower byte at
PCI Config space 0x08 is Device Revision and is read-only.
1.5 Device Internal Register Sets
The Device Configuration Registers and the four individual UART Configuration Registers of the V254
occupy 2K of PCI bus memory address space. These addresses are offset onto the basic memory address, a
value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. The
UART Configuration Registers are mapped into 4 address blocks where each UART channel occupies 512
bytes memory space for its own registers that include the 16550 compatible registers. The Device
Configuration Registers are embedded inside the UART channel zero’s address space between 0x0080 to
0x0093. All these registers can be accessed in 8, 16, 24 or 32 bits width depending on the starting address
given by the host at beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16,
24 or 32 bits format in special locations given in the Table 5 below. Every time a read or write operation is
made to the transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential
data location either in byte, word or dword. One special case applies to the receive data unloading when
reading the receive data together with its LSR register content. The host must read them in 16 or 32 bits format
in order to maintain integrity of the data byte with its associated error flags. These special registers are further
discussed in “Section 3.1, FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT” on page 26.
13