XR17V254_08 Datasheet, PDF (26/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.1
generators for standard or custom rates. Typically, the oscillator connections are shown in Figure 10. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
FIGURE 10. TYPICAL OSCILLATOR CONNECTIONS
R=300K to 400K
XTAL1 14.7456 XTAL2
MHz
C1
22-47pF
C2
22-47pF
3.0 TRANSMIT AND RECEIVE DATA
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel as shown in Table 5 set to ease
programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it increases the
data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in
the UART channel register is paired along with the data byte. This operation further facilitates data unloading
with the error flags without having to read the LSR register separately. Furthermore, the XR17V254 supports
PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the
data byte.
3.1 FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT
The XR17V254 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the individual channel’s register set) where the RX and the TX FIFO can be read from/
written to, as shown in Table 5. The following is an extract from the table showing the burstable memory
locations:
Channel N: (for channels 0 through 3) where M = 2N + 1.
RX FIFO
:
0xM00 - 0xM3F (64 bytes)
TX FIFO
:
0xM00 - 0xM3F (64 bytes)
RX FIFO + status
:
0xM80 - 0xMFF (64 bytes data + 64 bytes status)
For example, the locations for channel 2 are:
Channel 2:
RX FIFO
:
0x500 - 0x53F (64 bytes)
TX FIFO
:
0x500 - 0x53F (64 bytes)
RX FIFO + status
:
0x580 - 0x5FF (64 bytes data + 64 bytes status)
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