XR88C681J-F Datasheet, PDF (69/101 Pages) Exar Corporation – Two Full Duplex, Independent Channels

XR88C681
Whenever a transmitter is idle or inactive, the TXDn
output for that particular channel will be continuously
marking (at a logic “high”). However, just prior to the
transmission of a character, the transmitter alerts the
receiver by generating a “START” bit. The START bit is
basically the TXDn output toggling “low” for one bit period,
following an idle period or the STOP bit of the preceding
character. Immediately after transmission of the START
bit, the least significant bit of the character will be sent
first, followed by progressively more significant bits. If the
communication protocol calls for it, the Transmitter will
send a “parity” bit between the most significant bit of the
character and the STOP bit. Figure 36 presents the
waveform (format) of the transmitter (TXDn) output. In
this case, the transmitter is send 5D16, with 8-N-1
protocol (8 bits per character, No-parity, 1-Stop Bit).
TXDn
Transmitter Idle
or Stop Bit
1
0
1
1
1
0
1
0
Start Bit
Stop Bit
Figure 36. The Output Waveform of the Transmitter While Sending
5D₁₆ (8-N-1 Protocol).
The DUART can be programmed to generate an Interrupt
Request to the CPU by setting IMR[0] and IMR[4] for
Channels A, and B, respectively. In this case, the DUART
would generate an Interrupt Request anytime a
Transmitter THR and TSR are empty of characters. The
CPU can service this interrupt request by writing a
character to the empty THR.
The Transmitter can be enabled or disabled via the
Command Register (see Section B.2). If the command is
issued to disable the transmitter, while there are still
characters in the THR and TSR, the Transmitter will
continue transmitting all of the remaining data within the
THR and TSR, until they are completely empty of
characters. No new characters can be written to the THR
once the DISABLE TRANSMITTER command has been
issued.
G.2 Receiver (RSR and RHR
The function of the serial receiver is to receiver serial data
at the RXDn input; convert it to parallel data, where it can
be read by the CPU. The receiver is also responsible for
computing and checking parity, if parity is being used.
The receiver consists of the Receive Shift Register (RSR)
and a Receive Holding Register (RHR). The RHR is, in
essence, a three byte FIFO. The receiver receives data at
the RXDn pin, where it is processed through the RSR.
Afterwards, the data is converted to parallel format, and is
transferred to the RHR. This character is then processed
through the 3 bytes of FIFO. Once the received character
reaches the top of the FIFO, it can be “popped” or read by
the CPU; when it reads the RHR. Figure 37 depicts a
simplified drawing of the Receiver.
Rev. 2.11
69