XR88C681J-F Datasheet, PDF (44/101 Pages) Exar Corporation – Two Full Duplex, Independent Channels

XR88C681
awaiting “vector information” on the Data Bus, following
the assertion of -INTA. In this case (for this interrupt
mode), this “vector” information is the op-code for one of
the RESTART instructions (RST). The Z-80 CPU
supports up to eight different RST instructions (RST0 -
RST38H). These instructions are one-byte calls to
specific locations within the CPU’s memory space, where
the appropriate Interrupt service routine resides.
Table 12 presents a list of these RESTART instructions,
the op-codes and the corresponding RESTART
addresses.
Op-Code (hex)
C7
CF
D7
DF
E7
EF
F7
FF
Mnemonic
RST 0
RST 08
RST 10
RST 18
RST 20H
RST 28H
RST 30H
RST 38H
Restart
Address (hex)
0000
0008
0010
0018
0020
0028
0030
0038
Table 12. Z-80 CPU Restart Instructions
Used with Vectored Interrupts
Therefore, once the CPU receives the op-code for one of
these RESTART instructions, it will begin executing this
instruction by loading the Program Counter with the
appropriate “Restart” Address. Afterwards, program
control will be branched to the “Restart Address” location.
For Example:
If the op-code E7₁₆ is loaded onto the Data Bus during the
-INTA cycle, this op-code corresponds with the RST 20H
instruction and, the CPU will load 0020₁₆ into the program
counter and program control with branch to that location
in memory (see Table 12). The user is responsible for
insuring that the interrupt service routine begins at this
location in memory.
An example of a circuit realizing this form of interrupt
processing, while interfacing to the DUART, is presented
in Section C.6.1.2. This section discusses interfacing the
DUART to the 8080A CPU Module. This exact same
approach could be used with the Z-80 CPU, provide that
the DUART is operating in the I-Mode and that the Z-80 is
operating in Interrupt Mode 0.
Direct Interrupt Processing (Interrupt Mode 1)
The Z-80 P will operate in this interrupt mode if the “IM 1”
instruction has been executed. Whenever the -INT pin is
asserted by a peripheral device requesting an interrupt,
the CPU will complete its current instruction. Afterwards,
the program counter will automatically be loaded with a
memory location (pre-determined by the circuit design of
the Z-80 CPU device) and program control will be
branched to that location in system memory. In this case,
program control would branch to 0038₁₆ in memory. The
user is responsible for insuring that the appropriate
interrupt service routine is at that particular location in
memory. The Z-80 CPU module does not provide the
peripheral device with any sort of “Interrupt
Acknowledge”. The CPU just processes through the
Interrupt Service Routine, eliminates the cause(s) of the
interrupt request and returns to normal operation.
Peripheral Vectored Interrupt Processing
(Interrupt Mode 2)
The Z-80 P will operate in this interrupt mode if the “IM 2”
instruction has been executed. This interrupt “mode” is
very useful if the user wishes to connect the interrupt
request outputs of several peripherals to the one -INT
input of the Z-80 CPU. This interrupt mode allows the
interrupting device to identify itself at a certain time, just
prior to interrupt servicing.
Whenever the -INT pin is asserted by a peripheral device
requesting an interrupt, the CPU will continue to complete
its current instruction. Once this current instruction is
completed, the CPU Module will assert the -INTA signal to
inform the peripheral device that interrupt service is about
to begin. Once the interrupting peripheral device has
detected the -INTA pulse, it will place an “interrupt vector”
on the Data Bus. This interrupt vector will be read by the
CPU and the CPU will branch program control to the
location (referred to by the interrupt vector). Please note
that if the IEI input to the DUART (or Zilog peripheral
device) is “low” then the DUART (or Zilog peripheral
device) will be disabled from generating any interrupt
requests to the CPU.
An example of this approach is presented Figure 19. In
this case the XR88C681 DUART is configured to operate
in the Z-Mode and is interfaced to the Z-80 CPU. When
the DUART requires interrupt servicing, it will assert its
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