XR88C681J-F Datasheet, PDF (22/101 Pages) Exar Corporation – Two Full Duplex, Independent Channels

XR88C681
Receiver problems such as Parity Error (PE), Receiver
Overrun Error (OE), or Framing Error (FE). The DUART
also does not offer the user to ability to configure one of
the output ports to relay the occurrence of any of these
conditions. Therefore, unless the user is implementing
some sort of “Data Link Layer” error checking scheme
such as CRC, the user is advised to “validate” the
received data by frequently reading the Status Register;
and checking for any non-zero upper-nibble values. This
is especially the case if the user has set the Error Mode to
“Character” (MR1n[5] = 0).
C.6 Servicing DUART Interrupts
Interrupt servicing with the XR88C681 DUART falls into
two broad categories: I-Mode and Z-Mode. I-Mode has
historically been referred to as the “Intel” Mode. Likewise,
the Z-Mode has been referred to as the “Zilog” Mode.
When the DUART is operating in the Z-Mode, the DUART
will place an 8 bit “interrupt vector” on the data bus, to the
CPU, during the “Interrupt Acknowledge” or IACK cycle.
The CPU will read this interrupt vector from the Data Bus,
and determine (from the Interrupt Vector data) the
location of the appropriate interrupt service routine, in
system memory. Additionally, the Z-Mode gives the user
a hardware approach to prioritize the interrupt requests
among numerous peripheral devices. This phenomenon
is discussed in greater detail in Section C.6.2.
When the DUART is operating in the I-Mode, the DUART
will not provide any interrupt vector information to the
CPU, during the IACK cycle. Interrupt Vector information,
or any means to route program control to the appropriate
Interrupt Service Routine, is accomplished external to the
DUART.
The DUART will be in the I-Mode following power up or a
hardware reset. The user must invoke the “Set Z-Mode”
command, in order to command the DUART into the
Z-Mode.
Although the I-Mode has been referred to as the “Intel”
Mode, and the Z-Mode as the “Zilog” Mode; this does not
mean that the user should only operate the DUART in the
Z-Mode when interfacing a Zilog microprocessor, or in the
I-Mode when interfacing to an Intel microprocessor. The
division between I-Mode and Z-Mode is not necessary
along “corporate” lines. If you are interfacing the DUART
to the following microprocessors/ microcontrollers, then
the DUART must operate in the I-Mode.
D 8051 P
D 8080 CP
D 8085 P
D 68HC11 C
D Z-80 P (Interrupt Modes 0 and 1)
However, the DUART should be operating in the Z-Mode
when interfacing the following microprocessors/
microcontrollers.
D 8088 P
D 8086 P
D 80286 - 80486 Ps
D Pentium P
D Z-80 P (Interrupt Modes 2)
The next few sections will provide detailed discussions of
DUART/Microprocessor interfacing and interrupt
processing on each of the above-mentioned
microprocessors. From this discussion, a detailed
description of I-Mode Interrupt processing and Z-Mode
Interrupt processing will emerge.
C.6.1 I-Mode Interrupt Servicing
The DUART will be in the I-Mode following power up of the
IC, or a hardware reset. In general, a CPU interfacing to a
DUART operating in the I-Mode, will function as follows,
during interrupt servicing.
If the DUART requires interrupt service from the CPU, it
will asserts the -INTR pin to the CPU. Once the CPU has
detected the interrupt request, it will determine the
location of the appropriate interrupt service routine, and
will branch program control to that location. The CPU will
accomplish all of this without providing an “Interrupt
Acknowledge” signal or any further interaction with the
DUART. Once the CPU has eliminated the cause(s) of the
DUART’s interrupt request, the DUART will then negate
its -INTR pin. The CPU will then exit the “DUART”
interrupt service routine and will resume normal
processing.
In general there are two approaches that CPUs
commonly use to locate the appropriate interrupt service
routine, when interfaced with an I-Mode DUART.
D Direct Interrupt Processing
D (External) Vectored-Interrupt Processing
Direct Interrupt Processing
If a CPU employs “Direct Interrupt Processing” then once
the CPU has detected the interrupt request, and has
completed its current instruction, the CPU will branch
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