XR88C681J-F Datasheet, PDF (63/101 Pages) Exar Corporation – Two Full Duplex, Independent Channels

XR88C681
Input Port
IP0
IP1
IP2
IP3
IP4
IP5
Alternate Function(s)
Approach to Program Alternate Functions
-CTSA: Clear to Send (CTS) input for Channel A.
Note: this input is Active Low, for the CTS function
IP0 can be programmed to function as the -CTSA
input by setting MR2A[4] =1. For a more detailed
discussion on this function, please see Section
G.3.
-CTSB: Clear to Send (CTS) input for Channel B. IP1 can be programmed to function as the -CTSB
Note: This input is Active Low for the CTS function input by setting MR2B[4] =1. For a more detailed
discussion on this function, please see Section G.3.
CT_EX: Counter/Timer External Clock Input.
RXCB: External Clock input for Receiver
Channel B
IP2 can be programmed to function as the external
clock input for the Counter/Timer by setting
ACR[6:4] = [0, 0, 0]. For a more detailed discus-
sion into the effect of this action please see Section
D.2
IP2 can also be programmed to function as the
external clock input for the Receiver of Channel B
by setting CSRB[7:4] = [1, 1, 1, 0] for the 16X
Clock, or CSRB[7:4] = [1, 1, 1, 1] for the 1X Clock.
TXCA: External Clock input for Transmitter
Channel A
IP3 can be programmed to function as the external
clock input for the Transmitter of Channel A by set-
ting CSRA[3:0] = [1, 1, 1, 0] for the 16X Clock, or
CSRA[3:0] = [1, 1, 1, 1] for the 1X Clock.
RXCA: External Clock input for Receiver
Channel A
IP4 can be programmed to function as the external
clock input for the Receiver of Channel A by setting
CSRA[7:4] = [1, 1, 1, 0] for the 16X Clock, or
CSRA[7:4] = [1, 1, 1, 1] for the 1X Clock.
TXCB: External Clock input for Transmitter
Channel B
IP5 can be programmed to function as the external
clock input for the Transmitter of Channel B by set-
ting CSRB[3:0] = [1, 1, 1, 0] for the 16X Clock, or
CSRB[3:0] = [1, 1, 1, 1] for the 1X Clock.
Table 21. Listing of Alternate Function for the Input Port
E.2 Input Port Configuration Registers (IPCR)
Change of state detectors are provided for input pins IP0 through IP3. These inputs are sampled by the 38.4kHz output
of the BRG (2.4kbps x 16). A high-to-low or low-to-high transition at these input lasting at least two clock periods
(approximately 50 s) will guarantee that the corresponding bit in the input port change register (IPCR) will be set,
although it may be set by a change of state as short as 25 s. The bit format of the IPCR follows. The status bits in the
IPCR (IPCR[7:4]) are cleared when the register is read by the CPU. Any change of state can also be programmed to
generate an interrupt via the “Input Port Change of State” interrupt.
Bit 7
Delta IP3
0 = No
1 = Yes
Bit 6
Delta IP2
0 = No
1 = Yes
Bit 5
Delta IP1
0 = No
1 = Yes
Bit 4
Delta IP0
0 = No
1 = Yes
Bit 3
IP3
0 = Low
1 = High
Bit 2
IP2
0 = Low
1 = High
Bit 1
IP1
0 = Low
1 = High
Bit 0
IP0
0 = Low
1 = High
Rev. 2.11
Table 22. Input Port Configuration Register - IPCR
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