XR88C681J-F Datasheet, PDF (33/101 Pages) Exar Corporation – Two Full Duplex, Independent Channels

XR88C681
Input Name
RST 7.5
RST 6.5
RST 5.5
INTR
Trigger
Positive Edge Triggered
High Level Until Sampled
High Level Until Sampled
High Level Until Sampled
Priority
2
3
4
5
Type
Direct
Direct
Direct
External Vectored
Acknowledge
Signal?
None
None
None
-INTA = “Low”
Address (Hex)
003C
0034
002C
See Table 10
Table 11. 8085 CPU Maskable Interrupt Request Inputs and their Features
Direct Interrupts
The 8085 CPU inputs RST 7.5, RST 6.5, and RST 5.5 are
“Direct Interrupt” request inputs. Specifically, if any of
these inputs are asserted, then the program counter of
the CPU is, upon completion of the current instruction,
automatically loaded with a memory location
(pre-determined by the circuitry within the 8085 device),
and branches program control to that location. These
“Direct” interrupts do not provide the peripheral device
with any sort of “Interrupt Acknowledge”. Hence,
according to Table 11, if the RST 7.5 input were asserted,
the value “003C₁₆” would be loaded into the program
counter of the CPU, and program control would branch to
that location in memory. The user is responsible to insure
that the correct interrupt service routine begins at that
location in memory.
The 8085 CPU offers interrupt prioritization, within the set
of Maskable Interrupts. This priority is reflected Table 11.
It should be noted that these priority levels only apply to
“pending” interrupt request. Once a particular interrupt
has “left the queue” and is being serviced by the CPU, this
prioritization scheme no longer applies to that particular
interrupt. Consequently, it is possible that an RST 5.5
interrupt request could “interrupt” the interrupt service
routine for the higher priority RST 7.5 interrupt request.
Therefore, the user must guard against this phenomenon
in his/her firmware.
Table 11 also indicates that the 8085 CPU will support
“external” vectored interrupts. The manner and
commands that are used in external vectored interrupt
processing are identical to that presented for the 8080
CPU (see Section C.6.1.2).
Figure 10 and Figure 11 present two different
approaches that can be used to interface the XR88C681
DUART to the 8085 CPU.
Figure 10 presents a schematic where the DUART will
request a “Direct” RST 6.5 Interrupt to the 8085 CPU. In
this case, the Interrupt Service Routine for the DUART
must begin at 0034₁₆ in system memory. This is a very
simple interface technique, because there is no “Interrupt
Acknowledge” signal to route and interface.
Rev. 2.11
33