XR88C681J-F Datasheet, PDF (28/101 Pages) Exar Corporation – Two Full Duplex, Independent Channels

XR88C681
CPU, from a external crystal. The 8228 System
Controller is responsible for buffering the bi-directional
Data Bus. Additionally, since the 8080 CPU device does
not directly provide control bus signals, the 8228 Device is
responsible for translating signaling information, from the
8080A device, into the following Control Bus signals; in
order to access memory and peripheral devices.
-INTA - Interrupt Acknowledge
-MEMR - Memory Read
-MEMW - Memory Write
-IOR - Input Port Read
-IOW - Output Port Write
Figure 6 presents a schematic of the 8080A CPU Module.
TANK
OSC
PHI2 (TTL)
RDYIN
-RESIN
+12V
+5V
GND
GND
+5V
-5V
+12V
8224
Clock
Generator
8080A CPU
A0 - A15
HOLD
INT
INTE
-WR
DBIN
HDLA
1
D0
2
D1
WAIT
D2
D3
READY
D4
D5
RESET
D6
D7
SYNC
-STATUS STROBE
GND
+5V
-BUSEN
D0
D1
D2
D3
D4
8228 ^D5
System D6
Controller _D7
INTA
MEMR
MEMW
IOR
IOW
Figure 6. Schematic of 8080A CPU Module
8080A CPU Module Interrupt Structure
The “Interrupt Structure” of the 8080A CPU is described
here. The 8080A CPU device consists of two signals:
INTE and INT. Additionally, the 8228 Bi-Directional Bus
consists of a single output signal, -INTA. INTE is the
active-high Interrupt Enable output, and INT is the
active-high Interrupt Request input. If the “Enable
Interrupt” command has been invoked, the INTE output
will be “high” indicating that the 8080 CPU will honor
interrupt requests from peripherals. Whenever the INT
pin is asserted by a peripheral device requesting an
interrupt, the CPU will complete its current instruction.
After completion of this instruction, the CPU module will
assert -INTA via the 8228 Bi-Directional Bus Driver (U2)
by toggling -INTA “low”. -INTA is the active-low “Interrupt
Acknowledge” signal that the CPU module outputs in
order to initiate the process of interrupt servicing. The
8080A CPU module only supports “external”
Rev. 2.11
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