XR17V258_08 Datasheet, PDF (68/70 Pages) Exar Corporation – 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
TABLE OF CONTENTS
REV. 1.0.1
GENERAL DESCRIPTION ................................................................................................ 1
APPLICATIONS............................................................................................................................................... 1
FEATURES .................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XR17V258 ............................................................................................................................... 1
FIGURE 2. PIN OUT OF THE DEVICE.................................................................................................................................................. 2
ORDERING INFORMATION................................................................................................................................ 2
PIN DESCRIPTIONS ......................................................................................................... 3
FUNCTIONAL DESCRIPTION .......................................................................................... 8
PCI Local Bus Interface .............................................................................................................................................. 8
PCI Local Bus Configuration Space Registers ........................................................................................................... 8
Power Management Registers ................................................................................................................................... 8
EEPROM Interface ..................................................................................................................................................... 8
1.0 XR17V258 INTERNAL REGISTERS........................................................................................................ 9
FIGURE 3. THE XR17V258 REGISTER SETS..................................................................................................................................... 9
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................... 9
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ....................................................................................................... 10
1.2 POWER MANAGEMENT REGISTERS ............................................................................................................. 11
TABLE 2: POWER MANAGEMENT REGISTERS ................................................................................................................................... 11
1.2.1 POWER STATES AND POWER STATE TRANSITIONS OF THE V258 ..................................................................... 12
D0 State.................................................................................................................................................................... 12
D3hot State............................................................................................................................................................... 12
D3cold State ............................................................................................................................................................. 13
FIGURE 4. POWER STATE TRANSITIONS OF THE XR17V258............................................................................................................ 13
1.3 SPECIAL READ/WRITE REGISTER TO STORE USER INFORMATION ........................................................ 13
TABLE 3: SPECIAL READ/WRITE REGISTER ..................................................................................................................................... 13
1.4 EEPROM INTERFACE....................................................................................................................................... 14
TABLE 4: EEPROM ADDRESS DEFINITIONS .................................................................................................................................... 14
1.5 DEVICE INTERNAL REGISTER SETS ............................................................................................................. 14
TABLE 5: XR17V258 UART AND DEVICE CONFIGURATION REGISTERS ........................................................................................... 15
1.6 DEVICE CONFIGURATION REGISTERS ......................................................................................................... 17
TABLE 6: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ................................................................................... 17
TABLE 7: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT ............................................................................... 18
1.6.1 THE GLOBAL INTERRUPT REGISTER....................................................................................................................... 18
FIGURE 5. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3 .................................................................................. 19
TABLE 8: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING ..................................................................................................... 19
TABLE 9: UART CHANNEL [7:0] INTERRUPT CLEARING ................................................................................................................... 19
1.6.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-00-
00)................................................................................................................................................................................... 20
FIGURE 6. TIMER/COUNTER CIRCUIT............................................................................................................................................... 20
TABLE 10: TIMER CONTROL REGISTERS .................................................................................................................................... 21
TIMER OPERATION ................................................................................................................................................ 21
FIGURE 7. TIMER OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES .......................................................................................... 22
FIGURE 8. INTERRUPT OUTPUT (ACTIVE LOW) IN ONE-SHOT AND RE-TRIGGERABLE MODES............................................................ 23
1.6.3 8XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 23
1.6.4 REGA [15:8] (DEFAULT 0X00) RESERVED................................................................................................................ 23
1.6.5 RESET [23:16] (DEFAULT 0X00)................................................................................................................................. 23
1.6.6 SLEEP [31:24] (DEFAULT 0X00) ................................................................................................................................. 24
1.6.7 DEVICE IDENTIFICATION AND REVISION ................................................................................................................. 24
1.6.8 REGB REGISTER ......................................................................................................................................................... 25
1.6.9 MULTI-PURPOSE INPUTS AND OUTPUTS ................................................................................................................ 25
1.6.10 MPIO REGISTERS ...................................................................................................................................................... 25
FIGURE 9. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT ........................................................................................................... 26
2.0 CRYSTAL OSCILLATOR / BUFFER ..................................................................................................... 27
FIGURE 10. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................. 28
3.0 TRANSMIT AND RECEIVE DATA ......................................................................................................... 28
3.1 FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT. ..................................................................... 28
3.1.1 NORMAL RX FIFO DATA UNLOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700.......................................... 28
3.1.2 SPECIAL RX FIFO DATA UNLOADING AT LOCATIONS 0X180, 0X380, 0X580, AND 0X780 ................................. 29
3.1.3 TX FIFO DATA LOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700, 0X900, 0XB00, 0XD00, 0XF00 ............. 30
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-
I