XR17V258_08 Datasheet, PDF (26/70 Pages) Exar Corporation – 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
FIGURE 9. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT
MPIOINT [7:0]
INT
AND
Rising Edge
Detection
AND
REV. 1.0.1
1
MPIOLVL [7:0]
Read Input Level
0
MPIO
Pin [7:0]
MPIOINV [7:0]
(Input Inversion Enable =1)
MPIOLVL [7:0]
(Output Level)
MPIO3T [7:0]
(3-state Enable =1)
OR
MPIOSEL [7:0]
(Select Input=1, Output=0 )
MPIOCKT
MPIOINT [7:0] (default 0x00)
The MPIOINT register enables the multipurpose input pin interrupt. If an MPIO pin is selected by MPIOSEL as
an input, then it can be selected to generate an interrupt. MPIOINT bit[0] enables input pin MPIO0 for interrupt,
and bit [7] enables input pin 7. No interrupt is enable if the pin is selected to be an output. The interrupt is edge
sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after a read to
register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active LOW or
active HIGH. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it.
MPIOINT Register
Multipurpose Input/Output Interrupt Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOLVL [7:0] (default 0x00)
The MPIOLVL register controls the output pins and provides the input level status for the input pins. The status
of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 (default) sets
the output to LOW and a logic 1 sets the output pin to HIGH. The MPIO interrupt will clear upon reading this
register.
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