XR17V258_08 Datasheet, PDF (29/70 Pages) Exar Corporation – 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT

XR17V258
REV. 1.0.1
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
(channel 2),......., 0xF00 (channel 7). This operation is at least 16 times faster than reading the data in 64
separate 8-bit memory reads of RHR register (0x000 for channel 0, 0x200 for channel 1, 0x400 for channel
2,......, 0xE00 for channel 7).
READ RX FIFO,
WITH NO ERRORS
Read n+0 to n+3
Read n+4 to n+7
Etc.
BYTE 3
FIFO Data n+3
FIFO Data n+7
BYTE 2
FIFO Data n+2
FIFO Data n+6
BYTE 1
FIFO Data n+1
FIFO Data n+5
BYTE 0
FIFO Data n+0
FIFO Data n+4
Channel 0 to 7 ReceiveData in 32-bit alignment through the Configuration Register Address
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
3.1.2 Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and 0x780
The XR17V258 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2), ....., 0xF80 (channel 3). The
entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD
reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following
tables show this clearly.
READ RX FIFO,
WITH LSR ERRORS
Read n+0 to n+1
Read n+2 to n+3
Etc
BYTE 3
FIFO Data n+1
FIFO Data n+3
BYTE 2
LSR n+1
LSR n+3
BYTE 1
FIFO Data n+0
FIFO Data n+2
BYTE 0
LSR n+0
LSR n+2
Channel 0 to 7 Receive Data with Line Status Register in a 32-bit alignment through the Configuration
Register Address 0x0180, 0x0380, 0x0580, 0x0780, 0x0980, 0x0B80, 0x0D80 and 0x0F80
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
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