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XR17V258_08 Datasheet, PDF (13/70 Pages) Exar Corporation – 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
XR17V258
REV. 1.0.1
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
D3COLD STATE
The V258 enters the state when power is removed from the device. All context is lost in this state and the V258
does not support PME# in this state. When power is restored, PCI RST# must be asserted and the V258 will
return to the D0 Uninitialized state with a full PCI 3.0 compliant power-on reset sequence. The V258 will set all
its registers and outputs to the power-on defaults just as at initial power up. The system software must then
fully initialize and re-configure the V258 to place it in the D0 Active state.
FIGURE 4. POWER STATE TRANSITIONS OF THE XR17V258
Power on +
PCI RST#
D0
Uninitialized
Power on +
PCI RST#
D0
Active
D3cold
D3hot
VCC Removed
1.3 Special Read/Write Register to store User Information
This 32-bit register can be used to store user information and is writable only via the EEPROM. This is
implemented at an offset of 0x48 in the PCI Configuration Space immediately following the Power
Management Registers. This register can be used to store application-specific information which may be used
by the device driver to initialize the device appropriately.
TABLE 3: SPECIAL READ/WRITE REGISTER
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX)
0x48
31:0
EWR
User Information Writable only through EEPROM
0x00000000
NOTE: EWR=Read/Write from external EEPROM.
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