XR17V258_08 Datasheet, PDF (30/70 Pages) Exar Corporation – 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.1
3.1.3 Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700, 0x900, 0xB00, 0xD00, 0xF00
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2),
............, 0xD00 (channel 6) and 0xF00 (channel 7).
WRITE TX FIFO
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Write n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Write n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
Channel 0 to 7 Transmit Data in 32-bit alignment through the Configuration Register Address
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
Transmit Data Byte n+3
Transmit Data Byte n+2
Transmit Data Byte n+1
Transmit Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
The THR and RHR register address for channel 0 to channel 7 is shown in Table 11 below. The THR and RHR
for each channel 0 to 7 are located sequentially at address 0x0000, 0x0200, 0x0400, 0x0600, 0x0800,
0x0A000, 0x0C00 and 0x0E00. Transmit data byte is loaded to the THR when writing to that address and
receive data is unloaded from the RHR register when reading that address. Both THR and RHR registers are
16C550 compatible in 8-bit format, so each bus operation can only write or read in bytes.
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