XR17V258_08 Datasheet, PDF (44/70 Pages) Exar Corporation – 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.1
5.5.1 Interrupt Generation:
• LSR is by any of the LSR bits [4:1]. See IER bit [2] description on the previous page.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
• MSR is by any of the MSR bits [3:0].
• Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
• CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit [7] and selection on MCR bit [2].
• RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit [6] and selection on MCR bit [2].
• Wake-up indicator is when the UART wakes up from the sleep mode.
5.5.2 Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
• Xon or Xoff interrupt is cleared by a read to ISR register.
• Special character interrupt is cleared by a read to ISR or after the next character is received.
• RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
• Wake-up indicator is cleared by a read to the INT0 register.
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TABLE 15: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT
LEVEL BIT [5] BIT [4] BIT [3] BIT [2] BIT [1] BIT [0]
1
0
0
0
1
1
0 LSR (Receiver Line Status Register)
2
0
0
0
1
0
0 RXRDY (Received Data Ready)
3
0
0
1
1
0
0 RXRDY (Receive Data Time-out)
4
0
0
0
0
1
0 TXRDY (Transmitter Holding Register Empty)
5
0
0
0
0
0
0 MSR (Modem Status Register)
6
0
1
0
0
0
0 RXRDY (Received Xon/Xoff or Special character)
7
1
0
0
0
0
0 CTS#/DSR#, RTS#/DTR# change of state
X
0
0
0
0
0
1 None (default)
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 15). See “Section
5.5.1, Interrupt Generation:” on page 44 and “Section 5.5.2, Interrupt Clearing:” on page 44 for details.
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