XR17V258_08 Datasheet, PDF (41/70 Pages) Exar Corporation – 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT

XR17V258
REV. 1.0.1
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
4.7 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits [4:1]. Upon unloading the receive data byte from RHR, the receive FIFO
pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR
register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches
the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out
function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths
as defined by LCR bits [1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit [0].
4.7.1 Receiver Operation in non-FIFO Mode
FIGURE 17. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X Clock
(8XMODE Register)
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Flags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
4.7.2 Receiver Operation with FIFO
FIGURE 18. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
16X or 8X Sampling
Clock (8XMODE Reg.)
64 bytes by 11-
bit wide FIFO
Receive Data
Byte and Errors
Receive Data Shift Data Bit
Register (RSR)
Validation
Receive Data Characters
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Receive Data
FIFO
(64-byte)
Data falls to 40 ^{RTS#/DTR# re-asserts when data falls below}
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
FIFO Trigger=48 ^{RHR Interrupt (ISR bit-2) is programmed}
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
Receive
Data
Data fills to 56 ^{RTS#/DTR# de-asserts when data fills above}
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RXFIFO1
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