XRT4500 Datasheet, PDF (65/99 Pages) Exar Corporation – MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
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When E_232H (pin 55) is set to logic 0 in RS232 mode,
the transmitters are configured to operate in a special
high-speed RS232 mode that can drive loads of 3000Ω
in parallel with 1000pF at speeds up to 256 KHz.
5.0 INTERNAL CABLE TERMINATIONS
XRT4500 has fully integrated receiver and transmitter
cable terminations for high speed signals (RXD, TXD,
RXC, TXC, SCTE). Therefore, no external resistors
and/or switches are necessary to implement the prop-
er line termination. The schematic diagrams given in
Figures 26 and 27 show the effective receiver and
transmitter terminations respectively for each mode of
operation. When a specific electrical interface is se-
lected by M0, M1 and M2, the termination required for
that interface is also automatically chosen. The
XRT4500 eliminates double termination problems
and makes point to midpoint operation possible in the
V.11 mode by providing the option for disabling the in-
ternal input termination on high speed receivers.
6.0 OPERATIONAL SCENARIOS
Visualizing features such as clock/data inversion,
echoed clock, and loopbacks, in DTE and DCE
modes makes configuring the XRT4500 a non-trivial
task. A series of 48 system level application diagrams
located at the end of the data sheet called “Scenari-
os” assist users in understanding the benefits of
these different features. The internal XRT4500 con-
nections required for a particular scenario are made
through MUX1 and MUX2 that are shown on the
block diagrams given in Figures 2 and 3 respectively.
Table 8 contains the signal routing information versus
control input logic level for MUX1 and Table 9 con-
tains similar information for MUX2.
7.0 APPLICATIONS INFORMATION
Traditional interfaces either require different transmit-
ters and receivers for each electrical standard, or use
complicated termination switching methods to change
modes of operation. Mechanical switching schemes,
which are expensive and inconvenient, include relays,
and custom cables with the terminations located in
the connectors. Electrical switching circuits using
FETs are difficult to implement because the FET
must remain off when the signal voltage exceeds the
supply voltage and when the interface power is off.
The XRT4500 uses innovative, patented circuit de-
sign techniques to solve the termination switching
problem. It includes internal circuitry that may be con-
trolled by software to provide the correct terminations
for V.10 (RS423), V.11 (RS422), V.28 (RS232), and
V.35 electrical interfaces. The schematic diagrams
given in Figures 26 and 27 conceptually show the
switching options for the high-speed receiver input
and transmitter output terminations respectively. Ad-
ditionally, Tables 4 and 5 provide a summary of re-
ceiver and transmitter specifications respectively for
the different electrical modes of operation.
V.10 (RS423) Interface
Figure 28 shows a typical V.10 (RS423) interface.
This configuration uses an unbalanced cable to con-
nect the transmitter TXA output to the receiver RXA
input. The “B” outputs and inputs that are present on
the differential transmitters and receivers contained in
the XRT4500 are not used. The system ground pro-
vides the signal return path. The receiver input resis-
tance is 10 kΩ nominal and no other cable termina-
tion is normally used for the V.10 mode.
V.11 (RS422) Interface
Figure 29 shows a typical V.11 (RS422) interface. This
configuration uses a balanced cable to connect the
transmitter TXA and TXB outputs to the receiver RXA
and RXB inputs respectively. The XRT4500 includes
provisions for adding a 125 Ω terminating resistor for
the V.11 mode. Although this resistor is optional in the
V.11 specification, it is necessary to prevent reflections
that would corrupt signals on high-speed clock and data
lines. The differential receiver input resistance without
the optional termination is 20 kΩ nominal.
V.28 (RS232) Interface
Figure 28 shows a typical V.28 (RS232) interface.
This configuration uses an unbalanced cable to con-
nect the transmitter TXA output to the receiver RXA
input. The “B” outputs and inputs that are present on
the differential transmitters and receivers contained in
the XRT4500 are not used. The system ground pro-
vides the signal return path. The receiver “B” input is
internally connected to a 1.4 V reference source to
provide a 1.4 V threshold. The receiver input resis-
tance is 5 kΩ nominal and no other cable termination
is normally used for the V.28 mode.
V.35 Interface
Figure 30 shows a typical V.35 interface. This configu-
ration uses a balanced cable to connect the transmit-
ter TXA and TXB outputs to the receiver RXA and
RXB inputs respectively. The XRT4500 internal termi-
nations meets the following V.35 requirements. The
receiver differential input resistance is 100 Ω ± 10 Ω
and the shorted-terminal resistance (RXA and RXB
connected together) to ground is 150 Ω ± 15 Ω. The
transmitter differential output resistance is 100 Ω ± 10
Ω and the shorted-terminal resistance (TXA and TXB
connected together) to ground is 150 Ω ± 15Ω.
The junction of the 3 resistors (CMTX) on the transmit
termination is brought out to pins 61 and 66 for TX1
62