XRT4500 Datasheet, PDF (5/99 Pages) Exar Corporation – MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
áç
FIGURE 22. ILLUSTRATION OF A “2-CLOCK DTE/DCE” INTERFACE ............................................................................ 51
FIGURE 23. THE BEHAVIOR OF THE TXC AND TXD SIGNALS AT THE DCE AND DTE SCCS, (DATA RATE = 1.0MBPS, “DCE-
TO-DTE” PROPAGATION DELAY = 160NS, “DTE-TO-DCE” PROPAGATION DELAY = 160NS)............................ 52
FIGURE 24. THE BEHAVIOR OF THE TXC AND TXD SIGNALS AT THE DCE AND DTE SCCS (DATA RATE = 1.544MBPS, DCE-
TO-DTE PROPAGATION DELAY = 160NS, DTE-TO-DCE PROPAGATION DELAY = 160NS) ............................. 52
FIGURE 25. ILLUSTRATION OF THE “ECHO-CLOCK” FEATURE WITHIN THE XRT4500 ................................................... 53
FIGURE 26. ILLUSTRATION OF THE WAVE-FORMS, ACROSS A DCE/DTE INTERFACE, WHEN THE ECHO-CLOCK FEATURE
(WITHIN THE XRT4500) IS USED AS DEPICTED IN FIGURE 25........................................................................ 54
1.3.5 THE “2CK/3CK” (2-CLOCK/3-CLOCK MODE - ENABLE/DISABLE SELECT INPUT PIN) ..................................... 54
FIGURE 27. ILLUSTRATION OF THE DCE/DTE INTERFACE, WITH THE DCE MODE XRT4500 OPERATING IN THE “2-CLOCK”
MODE ........................................................................................................................................................ 55
1.3.6 THE “CLOCK INVERSION” (CK_INV) FEATURE ..................................................................................................... 55
FIGURE 28. ILLUSTRATION OF THE DCE MODE XRT4500 BEING CONFIGURED TO INVERT THE TXC SIGNAL................ 56
FIGURE 29. ILLUSTRATION OF THE DTE MODE XRT4500 BEING CONFIGURED TO INVERT THE TXC SIGNAL ................ 56
FIGURE 30. ILLUSTRATION OF THE DCE MODE XRT4500, WHICH IS OPERATING IN THE “2-CLOCK” MODE, AND INVERTING
THE “TXC” SIGNAL ..................................................................................................................................... 57
1.3.7 THE LATCH MODE OF OPERATION ........................................................................................................................ 58
1.3.8 THE REGISTERED MODE OF OPERATION ............................................................................................................. 58
FIGURE 31. AN ILLUSTRATION OF THE EFFECTIVE INTERFACE BETWEEN THE XRT4500 AND THE SCC/MICROPROCESSOR
WHEN THE “REGISTERED” MODE IS ENABLED ............................................................................................... 58
FIGURE 32. AN ILLUSTRATION OF THE NECESSARY GLUE LOGIC REQUIRED TO DESIGN A FEATURE SIMILAR TO THAT OFFERED
BY THE “REGISTERED” MODE, WHEN USING A DIFFERENT MULTI-PROTOCOL SERIAL NETWORK INTERFACE IC 59
1.3.9 THE INTERNAL OSCILLATOR .................................................................................................................................. 59
FIGURE 33. ILLUSTRATION OF THE INTERNAL OSCILLATORS WITHIN THE XRT4500..................................................... 60
1.3.10 GLITCH FILTERS...................................................................................................................................................... 60
1.3.11 DATA INVERSION .................................................................................................................................................... 60
1.3.12 DATA INTERLUDE ................................................................................................................................................... 60
2.0 RECEIVER AND TRANSMITTER SPECIFICATIONS .........................................................................60
3.0 V.10\V.28 OUTPUT PULSE RISE AND FALL TIME CONTROL .........................................................60
FIGURE 34. V.10 RISE/FALL TIME AS A FUNCTION OF RSLEW ................................................................................. 61
FIGURE 35. V.28 SLEW RATE OVER ± 3 V OUTPUT RANGE WITH 3 KW IN PARALLEL WITH 2500 PF LOAD AS A FUNCTION
OF RSLEW................................................................................................................................................ 61
4.0 THE HIGH-SPEED RS232 MODE ........................................................................................................61
5.0 INTERNAL CABLE TERMINATIONS ..................................................................................................62
6.0 OPERATIONAL SCENARIOS ..............................................................................................................62
7.0 APPLICATIONS INFORMATION .........................................................................................................62
FIGURE 36. RECEIVER TERMINATION ........................................................................................................................ 63
TABLE 6: RECEIVER SWITCHES ................................................................................................................................ 63
FIGURE 37. TRANSMITTER TERMINATION .................................................................................................................. 64
TABLE 7: TRANSMITTER SWITCHES........................................................................................................................... 64
FIGURE 38. TYPICAL V.10 OR V.28 INTERFACE (R1 = 10 KW IN V.10 AND 5 KW IN V.28) ........................................ 64
FIGURE 39. TYPICAL V.11 INTERFACE (TERMINATION RESISTOR, R1, IS OPTIONAL.).................................................. 64
FIGURE 40. TYPICAL V.35 INTERFACE ...................................................................................................................... 65
TABLE 8: MUX1 CONNECTION TABLE....................................................................................................................... 65
TABLE 9: MUX2 CONNECTION TABLE (RX4-RX7, TX4-TX7), OUTPUT VERSUS INPUT .............................................. 67
FIGURE 41. SCENARIO A, MUX2, (DCE/DTE = 0, LP = 0)....................................................................................... 68
FIGURE 42. SCENARIO B, MUX2, (DCE/DTE = 0, LP = 1), LOOP BACK NOT ENABLED ............................................. 69
FIGURE 43. SCENARIO C, MUX2, (DCE/DTE = 1, LP = 0)....................................................................................... 70
FIGURE 44. SCENARIO D, MUX2, (DCE/DTE = 1, LP = 1), LOOP BACK NOT ENABLED ............................................. 71
FIGURE 45. SERIAL INTERFACE SIGNALS AND CONNECTOR PIN-OUT ......................................................................... 72
FIGURE 46. SERIAL INTERFACE CONNECTOR DRAWINGS........................................................................................... 73
FIGURE 47. EIA-530 CONNECTION DIAGRAM FOR XRT4500 .................................................................................... 74
FIGURE 48. RS-232 CONNECTION DIAGRAM FOR XRT4500 ..................................................................................... 75
Scenarios 1 & 2 Normal: ‘3-clock’ DCE/DTE Interface Operation ...........................................................76
Input Pin Settings ....................................................................................................................................76
Scenario 3 &2 DTE Loop-Back Mode......................................................................................................77
Input Pin Settings ....................................................................................................................................77
Scenario 4 ...............................................................................................................................................78
Comments: DCE Loop-Back Mode .........................................................................................................78
II