XRT4500 Datasheet, PDF (56/99 Pages) Exar Corporation – MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
some digital Is, this amount of set-up time is marginal
and is likely to result in bit-errors. Throughout the re-
mainder of this document, this phenomenon will be
referred to as the “2-Clock/Propagation Delay” phe-
nomenon.
Cases 1 and 2 indicate that if a wide range of data
rates are to be supported by some Data Communica-
tion Equipment over a “2-Clock DTE/DCE” Interface'
and if the propagation delays are sufficiently large (in
the “DCE-to-DTE” and “DTE-to-DCE” link); then there
are some data rates that will be handled in an “error-
free” manner; and other data rates which are prone to
errors. Consequently, the “3-Clock DTE/DCE Inter-
face” is a much more robust and reliable medium to
transport data, than is the “2-Clock DTE/DCE” Inter-
face.
Using the “Echo-Clock” Feature within the
XRT4500
The “Echo-Clock” features within the XRT4500 helps
to mitigate the “2-Clock/Propagation Delay” phenom-
enon by forcing the DTE Mode XRT4500 to supply an
additional clock signal (over the DTE/DCE Interface),
over and above that provided by the DTE SCC.
Figure 25 presents an illustration of the “Echo Clock”
feature (within the DTE Mode XRT4500) being used.
FIGURE 25. ILLUSTRATION OF THE “ECHO-CLOCK” FEATURE WITHIN THE XRT4500
SCC (L)
TXD
DTE
DCE
63
TXD
78
60
TX1
62
RX1
1
79
SCC (R)
TXD_IN
SCTE
67
TX2
64
SCTE
77
65
76
RX2
74
SCTE_IN
TXC_IN
RXC_IN
RXD_IN
70
73
RX3
71
77
74
RX2
76
78
1
RX1
79
XRT4500
TXC
RXC
RXD
70
68
71
TX3
64
67
65
TX2
63
60
62
TX1
XRT4500
TXC
RXC
RXD
In the example, presented in Figure 25, the DTE SCC
does not supply the SCTE signal to the DTE/DCE In-
terface (just as in the two previous examples). How-
ever, in this case, the XRT4500 (on the DTE side) has
been configured to operate in the “Echo-Clock” Mode.
While the XRT4500 is operating in this mode, it will
simply take the “incoming” Transmit Clock signal
(TXC) and will “echo” it back to the SCTE input pin of
the DCE SCC. If we were to closely analyzer the
clock signals that are transported across the “DTE/
DCE” Interface, in order to determine the resulting
“TXC to TXD set-up time”, we would observe the fol-
lowing.
1. The DCE SCC sources the TXC clock signal to the
DTE node.
2. The DTE SCC will update the state of the TXD line
on the rising edge of the “incoming” TXC clock signal.
3. The “DTE” XRT4500 will “internally” route the
“RX3D” output signal to the TX2D output signal. As a
consequence, the incoming TXC clock signal will be
“echoed” back out to the SCTE input pin of the DCE
SCC.
4. If we neglect the “Clock-to-Output” delay of the
DTE SCC, the DCE SCC will receive the falling edge
of the SCTE clock signal, very close to the middle of
the bit-period of each bit on the TXD line.
This phenomenon is also illustrated below in
Figure 26.
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